2001 Fiscal Year Final Research Report Summary
Research on Branch Prediction and Speculative Execution
| Project/Area Number |
11680351
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Nagoya University |
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Principal Investigator |
SHIMODA Toshio Nagoya University, School of Eng., Professor, 工学研究科, 教授 (60252251)
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| Project Period (FY) |
1999 – 2001
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| Keywords | branch prediction / speculative execution / microprocessor / both-path execution / value prediction |
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| Research Abstract |
To design a higher performance microprocessor in the future, it is important to study branch prediction and speculative execution. In this research we set a goal to attain higher performance by combining two branch prediction mechanisms. We describe the results in the following.
Both-path ExecutionWe have evaluated the Both-path execution mechanism using SPECint95. The processor with 8-instruction issue, 2-ported instruction cache, 4-ported data cache, and five contexts have showed performance improvement 20.5% at the maximum and 1 1.2% on the average compared with a conventional single-path execution. A new mechanism of branch prediction using branch filtering achieves a maximum of 8.1% performance improvement comparing to that of conventional decision mechanism.
Branch Prediction using Value PredictionThis mechanism predicts values of operand and opcode and then predicts branch direction. This can be used with the conventional branch prediction mechanism in hybrid. We evaluate this mec
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hanism by using SPECint95 and get the result of 2.55% improvement at the maximum and 0.84% improvement on the average about prediction accuracy compared with a conventional 4K-byte gshare mechanism. This means that a current superscaler processor can improve performance by a maximum of 5.95% and 2.43% on the average. When we use the processor with a deeper pipeline and wider instruction issue, the performance improvement is 14.1% at the maximum and 6.0% on the average.
A Branch Prediction schemes that reduces Destructive Aliasing Using Branch Direction BiasThis mechanism (named sgshre) divides the pattern history table into two parts, and maps branches with the same direction bias to only a single part of the table. Sgshare converts destructive aliasing into harmless aliasing. Our evaluation shows that sgshare achieves 0.05-0.89% better prediction accuracy than the conventional gshare. This contributes to the performance of a current superscaler processor by 7. 19% and that ofa future superscaler processor with a wider instruction issue and a deeper pipeline by 1 4.6%. Less
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Research Products
(10 results)
