• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to project page

2002 Fiscal Year Final Research Report Summary

Development of Architectures and Design Methodologies of Customizable IP Cores for System-LSI's

Research Project

Project/Area Number 12358002
Research Category

Grant-in-Aid for Scientific Research (A)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 計算機科学
Research InstitutionKyushu University

Principal Investigator

MURAKAMI Kazuaki  Kyushu Univ., Faculty of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (10200263)

Co-Investigator(Kenkyū-buntansha) IWAIHARA Mizuho  Kyoto Univ., Grad. School of Informatics, Associate Professor, 大学院・情報学研究科, 助教授 (40253538)
MATSUNAGA Yusuke  Kyushu Univ., Faculty of ISEE, Associate Professor, 大学院・システム情報科学研究院, 助教授 (00336059)
YASUURA Hiroto  Kyushu Univ., Faculty of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (80135540)
TOMIYAMA Hiroyuki  Institute of System and Information Technology, Researcher, 第1研究室, 研究員(研究職)
INOUE Sozo  Kyushu Univ., Faculty of ISEE, Research Associate, 大学院・システム情報科学研究院, 助手 (90346825)
Project Period (FY) 2000 – 2002
Keywordssystem LSI / IP core / design methodology / design optimization / low power design / computer architecture / HW / SW codesign / dynamic optimization
Research Abstract

The objective of this research project is to develop architectures and design methodologies of customizable IP cores for system-LSI's. The project has performed the following research results.
(1) Development of customizable IP core architectures : The project has developed several customizable processors and co-processors as customizable IP cores, and design methodologies for these IP cores. The technologies developed include (I) customizable processors where the performance and energy consumption of their functional units can be (re)configured and optimized at either compile time or run time, (ii)customizable co-processors whose functionality and organization can be reconfigured at run time, (iii) online hardware synthesis technology which produces hardware configuration information for the customizable co-processors, and so on.
(2) Development of customizable memory core architectures : The project has developed several customizable memory cores and related technologies ; (I) customizing the instruction decoding for object programs, based on the statistical analysis on the appearance frequency of bit patterns of instructions, so that the power consumed for fetching instructions from a program ROM, (ii) customizing and reducing the number of tag lookups for instruction cache, based on the profile of instruction fetch addresses, so that the power consumed for checking the instruction cache tags, and so on.
(3) Development of customization techniques for variable-size datapath and memory-path : The project has developed some techniques for analyzing the dynamic ranges of variables in source programs, and then determining the size of datapath and memory-path so that tradeoff between the performance and power consumption can be achieved.

  • Research Products

    (31 results)

All Other

All Publications (31 results)

  • [Publications] K.Inoue et al.: "Omitting Cache Look-Up for High-Performance, Low-Power Microprocessors"IEICE Transactions on Electronics. E85-C・2. 279-287 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue et al.: "Trends in High-Performance, Low-Power Cache Memory Architectures"IEICE Transactions on Electronics. E85-C・2. 304-314 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue et al.: "A History-Based I-Cashe for Low-Energy Multimedia Applications"Proc. of International Symposium on Low Power Electronics and Design (ISLPED'02). 148-153 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y.Cao et al.: "Memory Organization for Low-Energy Processor-Based Application-Specific Systems"IEICE Transactions on Electronics. E85-C・8. 1616-1624 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y.Cao et al.: "Quality-Driven Design for Video Applications"IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Science. E85-A・12. 2568-2576 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y.Matsunaga: "An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs"IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Science. E85-A・12. 2715-2724 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Inoue, K., et al.: "Dynainically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs"IEICE Transaction on Information and Systems. E83-D. 1048-1057 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Inoue, A., et al.: "Flexible System LSI for Embedded Systems and Its Optimization Technques"Journal of Design Automation for Embedded Systems. 5 No2. 179-205 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Hashimoto, K., et al.: "PRAM-Link : A New High-Speed Communcation Interface Standard for Merged-DRAM/Logic System-on-a-Chip Architecture"SCI-Europe'2000. 67-78 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Yamashita, H., et al.: "Variable Size Analysis and Validation of Computation Quality"Proc. Workshop on High-Kevel Design Validation and Test (HLDVT'00). 95-100 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Inoue, K., et al.: "A High-Performance/Low-Power On-Chip Memory-Path rchitecture with Variable Cache-Line Size"IEICE Transactions on Electronics. E83-C. 1716-1723 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Yasuura, H., et al.: "Towards the System LSI Design Technology"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. E84-A. 91-97 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Inoue, K., et al.: "A Low-Power Instruction Cache Architecture Exploiting Program Execution Footprints"Proc. 7^<th> International Conference on High-Performance Computer Architecture. (CD-ROM). (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Murakami, K., et al.: "Trends in High-Performance, Low-Power Processor Architectures"IEICE Transactions on Electronics. E84-C. 131-138 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Okuma, T., et al.: "Software Energy Reduction Techniques for Variable Voltage Processors"IEEE Design & Test of Computers. 18. 31-41 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Inoue, K., Kai, K., and Murakami, K.: "Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs"IEICE Transactions on Information and Systems. vol.E83-D. 1084-1057 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Inoue, A., Ishihara, T., and Yasuura, H.: "Flexible System LSI for Embedded Systems and Its Optimization Techniques"Journal of Design Automation for Embedded Systems. vol.5, No.2. 179-205 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Hashimoto, K., Yamasaki, M., Tomita, H., Metsugi, K., and Murakami, K.: "PPRAM-Link : A New High-speed Communication Interface Standard for Merged-DRAM/Logic System-on-a-Chip Architecture"SCI-Europe'2000, Aug 2000. 67-78 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Yamashita, H., Yasuura, H., Eko, F.N., and Cao, Y.: "Variable Size Analysis and Validation of Computation Quality"Proc. Workshop on High-Level Design Validation and Test (HLDVTOO), Nov. 2000. 95-100 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Inoue, K., Kai, K., and Murakami, K.: "A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size"IEICE Transactions on Electronics. Vol.E83-C, No.11. 1716-1723 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Yasuura, H.: "Towards the System LSI Design Technology"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol.E84-A No.1. 91-97 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Inoue, K. and Murakami, K.: "A Low-Power Instruction Cache Architecture Exploiting Program Execution Footprints"Proc. 7th International Conference on High-Performance Computer Architecture, Jan. 2001. (CDROM).

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Murakami, K. and Magoshi, H.: "Trends in High-performance, Low-Power Processor Architectures"IEICE Transactions on Electronics. Vol.E84-C No.2. 131-138 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Okuma, T., Ishihara, T., and Yasuura, H.: "Software Energy Reduction Techniques for Variable Voltage Processors"IEEE Design & Test of Computers, March-April 2001. Vol.18, No.2. 31-41 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Inoue, K., Moshnyaga, V.G., and Murakami, K.: "Trends in High-Performance, Low-Power Cache Memory Architectures"IEICE Transactions on Electronics. Vol.E85-C No.2. 304-314 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Inoue, K., Moshnyaga, V.G., and Murakami, K.: "Omitting Cache Look-Up for High-Performance, Low-Power Microprocessors"IEICE Transactions on Electronics. Vol.E85-C No.2. 279-287 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Cao, Y., and Yasuura, H.: "Memory Organization for Low-Energy Processor-Based Application-Specific Systems"IEICE Transactions on Electronics. Vol.E85-C No.8. 1616-1624 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Inoue, K., Moshnyaga, V.G., and Murakami, K.: "A Low Energy Set-Associative I-Cashe with Extended BTB"Proc. 2002 International Conference on Computer Design, Sept. 2002. 187-192

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Cao, Y., and Yasuura, H.: "Quality-Driven Design for Video Applications"IEICE Transactions on Electronics. VolE.85-A No.8. 2568-2576 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Matsunaga, Y.: "An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs"IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Science. Vol.E85-A. 2715-2724 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K.Inoue et al.: "A History-Based I-Cashe for Low-Energy Multimedia Applications"Proc. Of International Symposium on Low Power Electronics and Design (ISLPED'02). 148-153 (2002)

    • Description
      「研究成果報告書概要(欧文)」より

URL: 

Published: 2004-04-14  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi