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2002 Fiscal Year Final Research Report Summary

Study on the Novel Single-Quantum Processing System using Single-Flux-Quantum Logic Circuits

Research Project

Project/Area Number 12450144
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionYokohama National University

Principal Investigator

YOSHIKAWA Nobuyuki  Yokohama National University, Faculty of Engineering, Associate Professor, 大学院・工学研究院, 助教授 (70202398)

Co-Investigator(Kenkyū-buntansha) KANEDA Hisayoshi  Yokohama National University, Faculty of Engineering, Research Associate, 大学院・工学研究院, 助手 (30242382)
Project Period (FY) 2000 – 2002
Keywordssingle flux quantum / SFO circuits / superconductor / Josephson device / integrated circuit / binary decision diagram / superconductivity electronics / microprocessor
Research Abstract

Single-flux-quantum (SFQ) logic circuits, which utilize an SFQ pulse in the superconducting circuits as a logical bit information, attract a great deal of attention recently because of their high-speed operating speed and low power dissipation compared with the semiconductor integrated circuits. Because the logical bit information in the SFQ circuits is represented by an SFQ, which is considered as a particle, we may build up a new type of logic operation system different from the conventional logic using me Boolean function.
The purpose of this study is to realize a single-quantum integrated system through the consideration of new SFQ logic circuits using a binary decision diagram (BDD), which is one kind of directional graphs.
In the research of 2001, we have optimized circuit parameters of the basic circuit cells for the BDD SFQ logic circuits and verified their operations. In 2002 we have designed and implemented the microprocessor components and investigated their functions in order to build a large-scale BDD SFQ logic circuit system. In 2003 we have designed the SFQ microprocessor prototype to investigate the feasibility of a large SFQ circuit system based on the asynchronous circuit design approach. The SFQ microprocessor designed is 8-bit bit-serial microprocessor having seven instructions. Its target clock frequency is 16 GHz. We have successfully confirmed the correct operations in all the circuit components, including register files, an ALU, a program counter and a controller.
These results show the feasibility of a large-scale SFQ logic circuit system as a high-end computing system in the next generation.

  • Research Products

    (38 results)

All Other

All Publications (38 results)

  • [Publications] 越山潤一, 吉川信行: "RSFQ論理回路のセルベース設計手法の検討"電子情報通信学会論文誌C. J83-C. 636-642 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 吉川信行, 森静香, 越山潤一: "Verilog HDLによるRSFQ論理回路のタイミング設計手法の検討"電子情報通信学会論文誌C. J83-C. 643-650 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Yoshikawa, J.Koshiyama: "Top-Down RSFQ Logic Design Based on a Binary Decision Diagram"IEEE Trans. Appl. Superconductivity. vol.11. 1098-1101 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] J.Koshiyama, N.Yoshikawa: "A Cell-Based Design Approach for RSFQ Circuits Based on Binary Decision Diagram"IEEE Trans. Appl. Superconductivity. Vol.11. 263-266 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Yoshikswa, T.Abe, Y.Kato, H.Hoshina: "Component Development for a 16 Gb/s RSFQ-CM0S Interface System"IEEE Trans. Appl. Superconductivity. vol.11. 735-738 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Yoshikawa, J.Koshiyama, K.Motoori, F.Matsuzaki, K.Yoda: "Cell-based top-down design methodology for RSFQ digital circuits"Physica C. 357-360. 1529-1539 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] A.Fujimaki, Y.Takai, N.Yoshikawa: "High-End Server Based on Complexity-Reduced Architecture for Superconductor Technology"IEICE Transactions on Electronics. E85-C. 612-616 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] F.Matsuzaki, K.Yoda, J.Koshiyama, K.Motoori, N Yoshikawa: "Design of small RSFQ Microprocessor based on Cell-Based Top-Down Design Methodology"IEICE Transactions on Electronics. E85-C. 659-664 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Yoshikawa, K.Yoda, H.Hoshina, F.Matsuzaki: "Cell-Based Design Methodology for BDD RSFQ Logic Circuits -Tolerance of Basic Cells to Circuit Parameter Variations"Supercond. Sci. Technol. 15. 156-160 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Van Duzer, L.Zheng, X.Meng, C.Loyo, S.R.Whiteley, L.Yu, N.Newman, J.M.Rowell, N.Yoshikawa: "Engineering issues in high-frequency RSFQ circuits"Physica C. 372-376. 1-6 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Yoshikawa, F.Matsuzaki, N.Nakajima, K.Yoda: "Design and Component Test of a 1-bit RSFQ Microprocessor"Physica C. 378-381. 1454-1460 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Fujiwara, H.Hoshina, J.Koshiyama, N.Yoshikawa: "Design and Component Test of RSFQ Packet Decoders for Shift Register Memories"Physica C. 378-381. 1475-1480 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Yoshikawa, K.Yoda, H.Hoshina, K.Kawasaki, K.Fujiwara, F.Matsuzaki, N.Nakajima: "Cell Based Design Methodology for BDD SFQ Logic Circuits : a High Speed Test and Feasibility for Large Scale Circuit Applications"IEEE Trans. Appl. Superconductivity. (to be published). (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Fujiwara, H.Hoshina, Y.Yamashiro, N.Yoshikawa: "Design and Component Test of SFQ Shift Register Memories"IEEE Trans. Appl. Superconductivity. (to be published). (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y.J.Feng, X.Meng, S.R.Whiteley, T.Van Duzer, K.Fujiwara, H.Miyakawa, N.Yoshikawa: "Josephson-CMOS hybrid memory with ultra-high-speed interface circuit"IEEE Trans. Appl. Superconductivity. (to be published). (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Yoshikawa, F.Matsuzaki, N.Nakajima, K.Fujiwara, K.Yoda, K.Kawasaki: "Design and Component Test of a Tiny Processor based on the SFQ Technology"IEEE Trans. Appl. Superconductivity. (to be published). (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] F.Matsuzaki, N.Yoshikawa, M.Tanaka, A.Fujimaki, Y.Takai: "A Behavioral-Level HDL Description of SFQ Logic Circuits for Quantitative Performance Analysis of Large-Scale SFQ Digital Systems"Physica C. (to be published). (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Fujiwara, H.Miyakawa, N.Yoshikawa, Y.Feng, S.R.Whiteley, T.Van Duzer: "Implementation and Low Speed Test of Ultra-Fast Interface Circuits for Josephson-CMOS Hybrid Memories"Physica C. (to be published). (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] M.Tanaka, T.Kondo, A.Sekiya, A.Fujimaki, H.Hayakawa, F.Matsuzaki, N.Yoshikawa, H.Terai, S.Yoroz: "Component test toward single-flux-quantum processors"Physica C. (to be published). (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] J. Koshiyama and N. Yoshikawa: "A Cell-Based Design Approach for RSFQ Circuits"IEICE Transactions on Electronics. 183-C, No.7. 636-642 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Yoshikawa, S. Mori, J. Koshiyama: "Timing Design of RSFQ Logic Circuits Using Verilog HDL"IEICE Transactions on Electronics. J83-C, No.7. 643-650 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Yoshikawa and J. Koshiyama: "Top-Down RSFQ Logic Design Based on a Binary Decision Diagram"IEEE Trans. Appl. Superconductivity. 11. 1098-1101 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] J. Koshiyama and N. Yoshikawa: "A Cell-Based Design Approach for RSFQ Circuits Based on Binary Decision Diagram"IEEE Trans. Appl. Superconductivity. 11. 263-266 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Yoshikawa, T. Abe, Y. Kato and H. Hoshina: "Component Development for a 16 Gb/s RSFQ-CMOS Interface System"IEEE Trans. Appl. Superconductivity. 11. 735-738 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Yoshikawa, J. Koshiyama, K. Motoori, F. Matsuzaki and K. Yoda: "Cell-based top-down design methodology for RSFQ digital circuits"Physica C.. 357-360. 1529-1539 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] A. Fujimaki, Y. Takai and N. Yoshikawa: "High-End Server Based on Complexity-Reduced Architecture for Superconductor Technology"IEICE Transactions on Electronics. E85-C, No.3. 612-616 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] F. Matsuzaki, K. Yoda, J. Koshiyama, K. Motoori and N. Yoshikawa: "Design of small RSFQ Microprocessor based on Cell-Based Top-Down Design Methodology"IEICE Transactions on Electronics. E85-C, No.3. 659-664 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Yoshikawa, K. Yoda, H. Hoshina and F. Matsuzaki: "Cell-Based Design Methodology for BDD RSFQ Logic Circuits -Tolerance of Basic Cells to Circuit Parameter Variations"Supercond. Sci. Technol.. 15. 156-160 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Van Duzer, L. Zheng, X. Meng, C. Loyo, S.R. Whiteley, L. Yu, N. Newman, J.M. Rowell, N. Yoshikawa: "Engineering issues in high-frequency RSFQ circuits"Physica C. 372-376. 1-6 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Yoshikawa, F. Matsuzaki, N. Nakajima and K. Yoda: "Design and Component Test of a 1-bit RSFQ Microprocessor"Physica C. 378-381. 1454-1460 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Fujiwara, H. Hoshina, J. Koshiyama, and N. Yoshikawa: "Design and Component Test of RSFQ Packet Decoders for Shift Register Memories"Physica C. 378-381. 1475-1480 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Yoshikawa, F. Matsuzaki, N. Nakajima, K. Fujiwara, K. Yoda and K. Kawasaki: "Design and Component Test of a Tiny Processor based on the SFQ Technology"IEEE Trans. Appl. Superconductivity.. to be published.

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Yoshikawa, K. Yoda, H. Hoshina, K. Kawasaki, K. Fujiwara, F. Matsuzaki, and N. Nakajima: "Cell Based Design Methodology for BDD SFQ Logic Circuits : a High Speed Test and Feasibility for Large Scale Circuit Applications"IEEE Trans. Appl. Superconductivity. to be published.

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Fujiwara, H. Hoshina, Y. Yamashiro, N. Yoshikawa: "Design and Component Test of SFQ Shift Register Memories"IEEE Trans. Appl. Superconductivity.. to be published.

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] YJ. Feng, X. Meng, S. R. Whiteley, T. Van Duzer, K. Fujiwara, H. Miyakawa, N. Yoshikawa: "Josephson-CMOS hybrid memory with ultra-high-speed interface circuit"IEEE Trans. Appl. Superconductivity.. to be published.

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] F. Matsuzaki, N. Yoshikawa, M. Tanaka, A. Fujimaki, Y. Takai: "A Behavioral-Level HDL Description of SFQ Logic Circuits for Quantitative Performance Analysis of Large-Scale SFQ Digital Systems"Physica C.. to be published.

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Fujiwara, H. Miyakawa, N. Yoshikawa, Y. Feng, S.R. Whiteley, T. Van Duzer: "Implementation and Low Speed Test of Ultra-Fast Interface Circuits for Josephson-CMOS Hybrid Memories"Physica C.. to be published.

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M. Tanaka, T. Kondo, A. Sekiya, A. Fujimaki, H. Hayakawa, F. Matsuzaki, N. Yoshikawa, H. Terai, S.Yorozu: "Component test toward single-flux-quantum processors"Physica C.. to be published.

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2004-04-14  

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