2002 Fiscal Year Final Research Report Summary
Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital Computing
| Project/Area Number |
12480064
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Tohoku University |
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Principal Investigator |
KAMEYAMA MICHITAKA Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (70124568)
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| Co-Investigator(Kenkyū-buntansha) |
HANYU TAKAHIRO Tohoku University, Research Institute of Electrical Communication, Professor, 電気通信研究所, 教授 (40192702)
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| Project Period (FY) |
2000 – 2002
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| Keywords | Dual-Rail Current-Mode Multiple-Valued Integrated Circuit / Logic-In-Memory VLSI / Source-Coupled Logic / Fine-Grain Pipelinign / Ferro-Electric Device / Nonvolatile Logic-in-Mmemory |
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| Research Abstract |
The communication bottleneck between memories and logic modules is one of the most serious problems due to interconnection complexity in recent deep-submicron VLSI systems-on-a-chip. In the situation, high-performance and low-power VLSI circuit technologies suitable for multi-giga-hertz clock operations are expected to be developed. In this study, we proposed multiple-valued VLSI utilizing differential-pair circuit which has high-driving capability and ferroelectric-capacitor logic for low-power logic-in-memory VLSI.
1.Development of the highest performance multiple-valued VLSI
A novel-source-coupled logic style using multiple-valued signals is proposed for high-speed-low-power VLSI system. All the differential-pair circuits are driven by dual-rail signals, which we call "full source-coupled logic". Design and implementation results show that the performance of the full-source coupled logic circuit is very superior to the conventional multiple-valued source-coupled logic circuit. It is a useful circuit technology for multi-gigahertz and low-voltage operations.
2.Ferroelectic Logic-in-Memory Architecture
A functional pass gate and a nonvolatile logic-in-memory architecture are proposed for communication-bottleneck-free VLSI system. Transition of a remnant-polarization charge and capacitive coupling of a ferroelectric capacitor makes storage and switching functions which are merged into a ferroelectric capacitor. The use of ferroelectric-based non-volatile storage makes leakage currents cut off. Applying the ferroelectric based circuitry to CAM implementation results in about half dynamic power reduction and 1/22000 static power reduction in comparison with the equivalent CMOS implementation under 0.6μm ferroelecric/CMOS process.
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