2001 Fiscal Year Final Research Report Summary
A Research of Register-less Architecture for Next Generation High Performance Processors
| Project/Area Number |
12480072
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
TOMITA Shinji Kyoto Univ., Graduate School of Informatics, Prof., 情報学研究科, 教授 (40026323)
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| Co-Investigator(Kenkyū-buntansha) |
NAKASHIMA Yasuhiko Kyoto Univ., Graduate School of Economics, Assoc.Prof., 経済学研究科, 助教授 (00314170)
MORI Shinichiro Kyoto Univ., Graduate School of Informatics, Assoc.Prof., 情報学研究科, 助教授 (20243058)
KITAMURA Toshiaki Kyoto Univ., Center for Information and Multimedia Studies, Assoc. Prof., 総合情報メディアセンター, 助教授 (10324683)
TSUMURA Tomoaki Kyoto Univ., Graduate School of Economics, Assoc., 経済学研究科, 助手 (00335233)
GOSHIMA Masahiro Kyoto Univ., Graduate School of Informatics, Assoc., 情報学研究科, 助手 (90283639)
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| Project Period (FY) |
2000 – 2001
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| Keywords | Dualflow / Wakeup / Select / JAVA / Value-Prediction / Value-Reuse / SPARC / Precomputation |
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| Research Abstract |
When a program is made to work on the various processors at high speed, the register-less architecture that explicitly handles registers becomes specifically important. We propose and evaluate an implementation technique that utilize more instruction-level parallelism and a function-level value reuse technique on our register-less architecture and the JAVA virtual machine.
(1) We propose and evaluate an register-less architecture which requires simple dynamic instruction scheduling hardware, because each instruction forwards it's result to following instructions explicitly. We also apply the technique against the ordinary superscalar processor and show that the proposed CAM based technique speed the cycle time two times as RAM based previous technique.
(2) We apply new implement technologies such as special purpose translation tables, instruction folding and value prediction against the JAVA virtual machine, and show that the maximum 29% of cycles could be reduced by instruction folding, maximum 42% of cycles could be reduces by value prediction respectively. We also propose a speculative clock control technique that reduce power consumption, and show 80% 〜 90% of power consumption could be reduced.
(3) We propose a function-level value reuse mechanism on the JAVA virtual machine which eliminate instructions itself completely without additional special instructions, and show that the maximum 47% of cycles could be reduced on SpecJVM98. We also apply these technique against SPARC architecture and show that the maximum 60% of cycles could be reduced on Stanford-integer.
(4) We propose the function-level precomputation processors which boost the normal value reuse, and show that the maximum 70% of cycles could be reduced against Stanford-integer programs that could not be speeds by simple value reuse.
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