2001 Fiscal Year Final Research Report Summary
Research on Mutithreaded Machine with Reconfigurable Hardware
| Project/Area Number |
12680326
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | University of Tsukuba |
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Principal Investigator |
YANAGUCHI Yoshinori University of Tsukuba, Institute of Information Sciences and Electrinics, Professor., 電子・情報工学系, 教授 (00312827)
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| Co-Investigator(Kenkyū-buntansha) |
KODAMA Yuetsu National Institute of Advanced Industrial Science and Technology, Grid Research Center, Senior Researcher, グリッド研究センター, 主任研究員 (80356998)
MAEDA Atsushi University of Tsukuba, Institute of Information Sciences and Electrinics,, 電子・情報工学系, 講師 (50293139)
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| Project Period (FY) |
2000 – 2001
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| Keywords | Mulththread / Reconfigurable device / FPGA / Encryption / Rijndael |
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| Research Abstract |
A fundamental research on developing an efficient multithreaded parallel architecture is studied. The special feature of this architecture is to combine the software threads and hardware functions totally and execute them efficiently. The reconfigurable device such as FPGA is a good candidate for implementing hardware functions which are compiled from software representations. Two topics are studied in this research. The first one is to evaluate the utilization of FPGA devices for this purpose. The crypt system is taken as one of the applications. The Rijndael crypt system which is selected as a new Advanced Encryption Standard (AES) is implemented and evaluated as a practical application on FPGA. The second one is to evaluate the effectiveness of translator from software representations to the hardware representations. A prototype of the translator is implemented which can translate sentences written in limited C language into the hardware representation in Verilog.
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