2003 Fiscal Year Final Research Report Summary
Development of High-performance Low-power Processor Systems
| Project/Area Number |
13023208
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| Research Category |
Grant-in-Aid for Scientific Research on Priority Areas
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| Allocation Type | Single-year Grants |
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| Review Section |
Science and Engineering
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| Research Institution | kyushu University |
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Principal Investigator |
YASUURA Hiroto Kyushu University, Graduate School of Information Science and Electrical Engineering, Professor, 大学院・システム情報科学研究院, 教授 (80135540)
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| Co-Investigator(Kenkyū-buntansha) |
SAWADA Sunao Kyushu University, Graduate School of Information Science and Electrical Engineering, Assistant Professor, 大学院・システム情報科学研究院, 助手 (70235464)
MATSUNAGA Yusuke Kyushu University, Graduate School of Information Science and Electrical Engineering, Associate Professor, 大学院・システム情報科学研究院, 助教授 (00336059)
MURAKAMI Kazuaki Kyushu University, Graduate School of Information Science and Electrical Engineering, Professor, 大学院・システム情報科学研究院, 教授 (10200263)
INOUE Sozo Kyushu University, Graduate School of Information Science and Electrical Engineering, Assistant Professor, 大学院・システム情報科学研究院, 助手 (90346825)
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| Project Period (FY) |
2000 – 2002
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| Keywords | High-performance Low-power / Datapath width optimization / Dynamic control of pipeline depth / Dynamic control of data-bus / Dynamic control of memory access bits |
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| Research Abstract |
In this research, we aim to develop constructing techniques for high-performance low-power processor systems, which combine software, architecture and circuit techniques such as processor and memory architectures, voltage control, and hardware software co-design. Although voltage, datapath width, and pipeline depth are not available in the past, we provide use of these parameters for designers of application-specific processor systems. In other words, this research is trying to provide means for designing high effective systems in large design space. This approach is the most progressive one in hardware software co-design techniques that have been researched and developed competitively in countries. We think that it is important to give these guidelines designers of application-specific processor systems. Proposed techniques can be summarized as follows
1)After analyzing the minimum bitwidth (effective bitwidth) for variables in programs, the datapath width is optimized for power efficiency processors or memories by using effective bitwidth.
2)The pipeline depth is dynamically controlled in consideration of characteristics of applications for low power.
3)Data bus and memory access bits are dynamically controlled to suppress power consumption of bits not transferring necessary information in datapath.
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Research Products
(12 results)
