2001 Fiscal Year Annual Research Report

高・強誘電体膜を用いた極低電圧・超低消費電力FET,及び高性能新機能素子の開発

Research Project

Project/Area Number	13025213
Research Category	Grant-in-Aid for Scientific Research on Priority Areas (A)
Research Institution	The University of Tokyo
Principal Investigator	平本俊郎東京大学, 大規模集積システム設計教育研究センター, 助教授 (20192718)
Co-Investigator(Kenkyū-buntansha)	石原宏東京工業大学, フロンティア創造共同研究センター, 教授 (60016657)
Keywords	半導体MOSFET / 低消費電力 / 基板バイパス / しきい値電圧 / 強誘電体ゲートFET / 不揮発生SRAM回路 / 強誘電体SPICEモデル / 低スタンバイ消費電力
Research Abstract	低電圧で動作する高性能の論理およびメモリデバイスの検討を行った.論理デバイスでは,基板バイアス効果によりしきい値電圧を変化させ,高速性と低消費電力を両立できるVTCMOS回路形式を検討した.この回路に用いるデバイスは,従来型のMOSFETとは異なり,印加する基板バイアスに臨界電圧以上の場合は基板バイアス定数が大きいほど特性が向上することを明らかにした.この臨界電圧はデバイスの微細化とともにスケールされるため,将来にわたってVTCMOS回路は有効である.また,縦積み回路においても基板バイアス定数が大きい方が有利であることを示した.一方,メモリデバイスでは,強誘電体キャパシタを用いたSRAM回路及びラッチ回路において,記憶保持の安定性と低スタンバイ消費電力が両立できる最適な回路構成の検討を行った.まず,強誘電体キャパシタのSPICEモデルを作成し,電界-分極特性や分極反転電流の時間依存性が良好に表現できることを明らかにし,このモデルによる次世代強誘電体メモリセルの動作シミュレーションと実際に作製したセルの動作の比較から従来のものよりもモデルの精度が高いこと、計算時間もそれ程長くならないことなどを明らかにした。次にこのシミュレータを用いて,ラッチ回路の最適構成について検討した結果,インバータのp-MOSおよびn-MOSのゲートにそれぞれ強誘電体キャパシタを接続する回路構成よりも,両ゲートを短絡した後に共通の強誘電体キャパシタを接続した構成の方が安定な特性が得られることを明らかにした.また,低電圧動作可能な強誘電体ゲートFETのゲート材料の探索を行なった.

Research Products

(15 results)

All Other

All Publications (15 results)

[Publications] T.Hiramoto, M.Takamiya, H.Koura, T.Inukai, H.Gomyo, H.Kawauchi, T.Sakurai: "Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)"Japanese Journal of Applied Physics. Vol.40,Part1, No.4B. 2854-2858 (2001)
[Publications] M.Takamiya, T.Hiramoto: "High Drive-Current Electrically Induced Body Dynamic Threshold SOI MOSFET (EIB-DTMOS) with Large Body Effect and Low Threshold Voltage"IEEE Transactions on Electron Devices. Vol.48,No.8. 1633-1640 (2001)
[Publications] T.Saito, T.Saraya, T.Inukai, H.Majima, T.Nagumo, T.Hiramoto: "Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs"IEICE Transactions on Electronics. (to be published). (2002)
[Publications] T.Inukai, H.Im, T.Hiramoto: "Origin of Critical Substrate Bias in Variable Threshold Voltage CMOS"Japanese Journal of Applied Physics. Vol.41,Part1,No.4B(to be published). (2002)
[Publications] X.Wang, H.Ishiwara: "Improvement of electrical property of Sol-gel derived lead zircone titanate thin films by multiple rapid thermal annealing"Japanese Journal of Applied Physics. <40>Part1.No.12. 7002-7006 (2001)
[Publications] X.Wang, H.Ishiwara: "Sol-gel derived ferroelectric Pb(Zr1-XTiX)O3-SiO2-B2O3 glass-ceramic thin films formed at relatively low annealing temperatures"Japanese Journal of Applied Physics. <40>[9B]. 5547-5550 (2001)
[Publications] S-M.Yoon, H.Ishiwara: "Memory operations of 1T2C-type ferroelectric memory cell with excellent date retention characteristics"IEEE Trans. on Electron Devices. Vol.48,No.9. 2002-2008 (2001)
[Publications] B-E.Park, H.Ishiwara: "Electrical properties of LaAlO3/Si and Sr0.8Bi2.2Ta2O9/LaAlO3/Si structure"Appl. Phys. Lett. Vol.79,No.6. 806-808 (2001)
[Publications] S.Ogasawara, S-M.Yoon, H.Ishiwara: "Fabrication and characterzation of 1T2C-type ferroelectric memory cell"IEICE Trans. on Electronics. Vol.84-C, No.6. 771-776 (2001)
[Publications] N.Ogata, H.Ishiwara: "A model for high frequency C-V characteristics of ferroelectric capacitors"IEICE Trans. on Electronics. Vol.84-C, No.6. 777-784 (2001)
[Publications] T.Tamura, A.Arimoto, H.Ishiwara: "A paeallel element model for simulation switching response of ferroelectric capacitors"IEICE Trans. on Electronics. Vol.84-C, No.6. 785-790 (2001)
[Publications] S-M.Yoon, H.Ishiwara: "Write and read-out operation of novel 1T2C-type ferroelectric memory cells with an array structure"Jpn. J. Appl. Phys.. Vol.40,Part2, No.5A. L449-L452 (2001)
[Publications] T.Kijima, Y.Fujisaki, H.Ishiwara: "Fabrication and characterization of Pt/(Bi, La)4Ti3O12/Si3N4/Si metal-ferroelectric-insulator-semiconductor structure for FET-type ferroelectric memory applications"Jpn. J. Appl. Phys. Vol.40,Part1, No.4B. 2977-2982 (2001)
[Publications] S.Yamamoto, T.Kato, H.Ishiwara: "A novel simulation program with integrated circuit emphasis(SPICE) model of ferroelectric capacitors using Schmitt-trigger circuit"Jpn. J. Appl. Phys.. Vol.40,Part1,No.4B. 2928-2934 (2001)
[Publications] E.Tokumitsu, K.Okamoto, H.Ishiwara: "Low voltage operation of nonvolatile metal-ferroelectric-metal-insulator-semiconductor(MFTJS)-field-effect-transistors (FETs) using Pt/SrBi2Ta2O9/Pt/SrTa2O6/SiON/Si structures"Jpn. J. Appl. Phys.. Vol.40,Part1,No.4B. 2911-2916 (2001)

2001 Fiscal Year Annual Research Report

高・強誘電体膜を用いた極低電圧・超低消費電力FET,及び高性能新機能素子の開発

Principal Investigator

平本 俊郎 東京大学, 大規模集積システム設計教育研究センター, 助教授 (20192718)

Research Products

[Publications] T.Hiramoto, M.Takamiya, H.Koura, T.Inukai, H.Gomyo, H.Kawauchi, T.Sakurai: "Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)"Japanese Journal of Applied Physics. Vol.40,Part1, No.4B. 2854-2858 (2001)

[Publications] M.Takamiya, T.Hiramoto: "High Drive-Current Electrically Induced Body Dynamic Threshold SOI MOSFET (EIB-DTMOS) with Large Body Effect and Low Threshold Voltage"IEEE Transactions on Electron Devices. Vol.48,No.8. 1633-1640 (2001)

[Publications] T.Saito, T.Saraya, T.Inukai, H.Majima, T.Nagumo, T.Hiramoto: "Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs"IEICE Transactions on Electronics. (to be published). (2002)

[Publications] T.Inukai, H.Im, T.Hiramoto: "Origin of Critical Substrate Bias in Variable Threshold Voltage CMOS"Japanese Journal of Applied Physics. Vol.41,Part1,No.4B(to be published). (2002)

[Publications] X.Wang, H.Ishiwara: "Improvement of electrical property of Sol-gel derived lead zircone titanate thin films by multiple rapid thermal annealing"Japanese Journal of Applied Physics. <40>Part1.No.12. 7002-7006 (2001)

[Publications] X.Wang, H.Ishiwara: "Sol-gel derived ferroelectric Pb(Zr1-XTiX)O3-SiO2-B2O3 glass-ceramic thin films formed at relatively low annealing temperatures"Japanese Journal of Applied Physics. <40>[9B]. 5547-5550 (2001)

[Publications] S-M.Yoon, H.Ishiwara: "Memory operations of 1T2C-type ferroelectric memory cell with excellent date retention characteristics"IEEE Trans. on Electron Devices. Vol.48,No.9. 2002-2008 (2001)

[Publications] B-E.Park, H.Ishiwara: "Electrical properties of LaAlO3/Si and Sr0.8Bi2.2Ta2O9/LaAlO3/Si structure"Appl. Phys. Lett. Vol.79,No.6. 806-808 (2001)

[Publications] S.Ogasawara, S-M.Yoon, H.Ishiwara: "Fabrication and characterzation of 1T2C-type ferroelectric memory cell"IEICE Trans. on Electronics. Vol.84-C, No.6. 771-776 (2001)

[Publications] N.Ogata, H.Ishiwara: "A model for high frequency C-V characteristics of ferroelectric capacitors"IEICE Trans. on Electronics. Vol.84-C, No.6. 777-784 (2001)

[Publications] T.Tamura, A.Arimoto, H.Ishiwara: "A paeallel element model for simulation switching response of ferroelectric capacitors"IEICE Trans. on Electronics. Vol.84-C, No.6. 785-790 (2001)

[Publications] S-M.Yoon, H.Ishiwara: "Write and read-out operation of novel 1T2C-type ferroelectric memory cells with an array structure"Jpn. J. Appl. Phys.. Vol.40,Part2, No.5A. L449-L452 (2001)

[Publications] T.Kijima, Y.Fujisaki, H.Ishiwara: "Fabrication and characterization of Pt/(Bi, La)4Ti3O12/Si3N4/Si metal-ferroelectric-insulator-semiconductor structure for FET-type ferroelectric memory applications"Jpn. J. Appl. Phys. Vol.40,Part1, No.4B. 2977-2982 (2001)

[Publications] S.Yamamoto, T.Kato, H.Ishiwara: "A novel simulation program with integrated circuit emphasis(SPICE) model of ferroelectric capacitors using Schmitt-trigger circuit"Jpn. J. Appl. Phys.. Vol.40,Part1,No.4B. 2928-2934 (2001)

[Publications] E.Tokumitsu, K.Okamoto, H.Ishiwara: "Low voltage operation of nonvolatile metal-ferroelectric-metal-insulator-semiconductor(MFTJS)-field-effect-transistors (FETs) using Pt/SrBi2Ta2O9/Pt/SrTa2O6/SiON/Si structures"Jpn. J. Appl. Phys.. Vol.40,Part1,No.4B. 2911-2916 (2001)

平本俊郎東京大学, 大規模集積システム設計教育研究センター, 助教授 (20192718)