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2003 Fiscal Year Final Research Report Summary

Development of "Hardware Morphing" Technology for Dynamic Optimization of Hardware Configuration

Research Project

Project/Area Number 13308015
Research Category

Grant-in-Aid for Scientific Research (A)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionKyushu University

Principal Investigator

MURAKAMI Kazuaki  Kyushu University, Faculty of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (10200263)

Co-Investigator(Kenkyū-buntansha) MATSUNAGA Yusuke  Kyushu University, Faculty of ISEE, Associate Professor, 大学院・システム情報科学研究院, 助教授 (00336059)
FUKUDA Akira  Kyushu University, Faculty of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (80165282)
YASUURA Hiroto  Kyushu University, Faculty of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (80135540)
INOUE Sozo  Kyushu University, Faculty of ISEE, Research Associate, 大学院・システム情報科学研究院, 助手 (90346825)
IWAIHARA Mizuho  Kyoto Univ., Grad.School of Informatics, Associate Professor, 大学院・情報学研究科, 助教授 (40253538)
Project Period (FY) 2001 – 2003
Keywordssystem LSI / dynamic optimization / computer architecture / profiling / low power design / optimizing compiler / adaptive control / circuit design
Research Abstract

The objective of this research project is to develop techniques(called "Syste Morph : System Morphing") of dynamic reconfiguration and optimization of hardware for system-LSI's and software for them, as (a)an approach for optimization of designing system-LSI's and (b)a solution for "design crisis". The project has performed the following research results.
(1)Development and evaluation of online-pro filing techniques : The project has developed some techniques of online profiling which find a hot spot(for example, programming codes, data, or paths operated frequently in a program) by observing the behavior of a program. Then, the project has implemented the online profile to the, dynamically-reconfigurable processor, DAP/DNA, by IPFlex, and evaluated its accuracy and overheads.
(2)Development and evaluation of dynamic-software-pipelining techniques : The project has developed some techniques of dynamic software pipelining for loops in the hot path found in (1). Then, the project has implemented the techniques for a hyper-scalar processor which has a VLIW as its coprocessor, and evaluated its improvement and overheads.
(3)Development and evaluation of online-construction techniques for configuration data of hardware : The project has developed some techniques to construct the configuration data of a DNA dynamically and in a parallel with the operation of the program, to con figure dynamically the hot path in (1) to the DNA as a logical circuit. Then, the project has implemented the techniques and valuated its performance

  • Research Products

    (26 results)

All Other

All Publications (26 results)

  • [Publications] H.Akaboshi et al.: "Case Study : Mapping Telecommunication Functions to Fine Grain Multiprocessor System (FPSA)"Proc.of International Symposium on Low-Power and High-Speed Chips (COOL Chips IV). 345 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Okuma et al.: "A System-level Energy Minimization Approach Using Datapath Width Optimization"IEEE Design & Test of Computers. 18・2. 32-41 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y.Cao et al.: "Software Energy Reduction Techniques for Variable Voltage Processors"Proc.of International Symposium on Low Power Electronics and Design (ISLPED'01). 231-236 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue et al.: "Dynamic Tag-Check Omission : A Low-Power Instruction Cache Architecture Exploiting Execution Footprints"Proc.of Workshop on Power Aware Computer Systems (PACS'02). 15-21 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue et al.: "Omitting Cache Look-Up for High-Performance, Low-Power Microprocessors"IEICE Transactions on Electronics. E85-C(2). 279-287 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue et al.: "Trends in High-Performance, Low-Power Cache Memory Architectures"IEICE Transactions on Electronics. E85-C(2). 304-314 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue et al.: "A History-Based I-Cashe for Low-Energy Multimedia Applications"Proc.of International Symposium on Low Power Electronics and Design (ISLPED'02). 148-153 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue et al.: "A Low Energy Set-Associative I-Cashe with Extended BTB"Proc.of International Conference on Computer Design (ICCD'02). 187-192 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue et al.: "Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality"IEICE Trans.FUNDAMENTALS. 86-A(4). 799-805 (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.Goulart et al.: "Dynamic Effective Precision Matching Computation"Proc.The 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2003). 230-237 (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Hayashida et al.: "Evaluating Online Hot Instruction Sequence Profilers for Dynamically Reconfigurable Functional Units"IEICE Trans.Information and Systems. E86-D(5). 901-909 (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Metsugi et al.: "Relaxing Constraints due to Data and Control Dependences"IEICE Trans.Information and Systems. E86-D(5). 920-928 (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Hayashida et al.: "Evaluating Online Hot Instruction Sequence Profiler Using Jumble-Counting Method"Proc.International Symposium on Information Science and Electrical Engineering 2003 (ISEE2003). 55-58 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H.Akaboshi et al.: "Case Study : Mapping Telecommunication Functions to Fine Grain Multiprocessor System(FPSA)"Proc.of International Symposium on Low-Power and High-Speed Chips(COOL Chips IV). 345 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T.Okuma et al.: "Software Energy Reduction Techniques for Variable Voltage Processors"IEEE Design & Test of Computers. 18(2). 32-41 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y.Cap et al.: "A System-level Energy Minimization Approach Using Datapath Width Optimization"Proc.of International Symposium on Low Power Electronics and Design (ISLPED'01). 231-236 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K.Inoue, et al.: "Dynamic Tag-Check Omission : A Low-Power Instruction Cache Architecture Exploiting Execution Footprints"Proc.of Workshop on Power Aware Computer Systems(PACS'02). 15-22 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K.Inoue, et al.: "Omitting Cache Look-Up for High-Performance, Low-Power Microprocessors"IEICE Transactions on Electronics. 279-287 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K.Inoue, et al.: "Trends in High-Performance, Low-Power Cache Memory Architectures"IEICE Transactions on Electronics. 304-314 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K.Inoue, et al.: "A History-Based I-Cashe for Low-Energy Multimedia Applications"Proc.of International Symposium on Low Power Electronics and Design (ISLPED'02). 148-153 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K.Inoue, et al.: "A Low Energy Set-Associative I-Cashe with Extended BTB"Proc.of International Conference on Computer Design(ICCD'02). 187-192 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K.Inoue, et al.: "Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality"IEICE Trans.FUNDAMENTALS. 86-A(4). 799-805 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V.Goulart, et al.: "Dynamic Effective Precision Matching Computation"Proc.The 11th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI 2003). 230-237 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T.Hayashida, et al.: "Evaluating Online Hot Instruction Sequence Profilers for Dynamically Reconfigurable Functional Units"IEICE Trans.Information and Systems. E86-D(5). 901-909 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K.Metsugi, et al.: "Relaxing Constraints due to Data and Control Dependences"IEICE Trans.Information and Systems. E86-D(5). 920-928 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T.Hayashida, et al.: "Evaluating Online Hot Instruction Sequence Profiler Using Jumble-Counting Method"Proc.International Symposium on Information Science and Electrical Engineering 2003(ISEE2003). 55-58 (2003)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2005-04-19  

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