| Research Abstract |
In this work, we proposed a design method for locally timed VLSI systems in terms of a scalable delay insensitive (SDI) model. In the SDI model, although unbounded gate and wire delays are assumed, the relative delay information among gates and wires is obtained. Therefore, by using such an information, area and performance optimum VLSI systems can be designed. In addition, we developed the CAD system named AINOS and the design library to facilitate out proposed design method. In AINOS, a Verilog RTL description is accepted as the input and corresponding asynchronous system is synthesized. During the synthesis, pairs of handshake signals to realize asynchronous communication are inserted, circuits to control handshake signals are generated, and the timing verification for handshake signals is realized. Since AINOS accepts the same description used in commonly used synchronous system designs, one can design locally timed systems easily if he is familiar with the Verilog description.
Together with AINOS development, we proposed several methods for the logic synthesis of locally timed VLSI systems. At first, to solve the wire delay problem, we proposed a design method so that the interface of circuits is insensitive to wire delays. As a result, the circuit can correctly operate under arbitrary wire delay for input wires. Next, to optimize asynchronous control circuits, we extended a boolean optimization method named transduction method to apply it for asynchronous control circuits. At last, we proposed a design method of control circuits to control data-path circuits with variable delay arithmetic units.
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