2003 Fiscal Year Final Research Report Summary
Study on High-Performance Low-Power Chip Multiprocessors
| Project/Area Number |
13480077
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | The University of Tokyo |
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Principal Investigator |
SAKAI Shuichi The University of Tokyo, Graduate School of Information Science and Technology, Professor, 大学院・情報理工学系研究科, 教授 (50291290)
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| Co-Investigator(Kenkyū-buntansha) |
SHIMIZU Shu The University of Tokyo, Graduate School of Information Science and Technology, Research Associate, 大学院・情報理工学系研究科, 助手 (20011182)
TANAKA Hidehiko The University of Tokyo, Graduate School of Information Science and Technology, Professor, 大学院・情報理工学系研究科, 教授 (60011102)
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| Project Period (FY) |
2001 – 2003
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| Keywords | Chip Multiprocessor / Low Power Architecture / Coherent Cache / Power Simulator / Speculative Multithreading / Performance Evaluation / Thread Prediction / Optimizing Compiler |
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| Research Abstract |
We studied high-performance low-power chip multiprocessors and obtained the following results.
(1) System level power reduction
We examined the power estimation framework which calculates the power consumption from the architecture description. The framework has high extensibility and flexibility. It can reduce the cost of designing low power processor chips. In addition, it makes easy the evaluations of the power reduction techniques. We also studied the elementary technologies for power reduction of chip multiprocessors. One of the most important elements is a cache, where we proposed the power reduction technique, evaluated it and showed its effectiveness.
(2) Performance improvement by speculative multithreading
We intensively studied the speculative multithreading, for improving the performance of sequential programs and extracting the maximum power of chip multiprocessors. We proposed and evaluated the innovative speculative multithreading on the following points (1) speculative execution for dependent activities; (2) thread fusion for reducing thread invocation/termination overhead; (3) register communication mechanisms suitable for thread speculations; (4) prediction mechanisms for efficient speculations; and (5) compiler support. For detailed design and feasibility studies, we have built a cycle level simulator of the chip multiprocessor and a C compiler for it, and closely evaluated each technology. The results showed the substantial performance improvement.
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