2003 Fiscal Year Final Research Report Summary
A Study on How Implementing Microprocessors Exploiting Instruction Level Parallelism
| Project/Area Number |
13558030
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
計算機科学
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
SATO Toshinori Kyushu Institute Of Technology, Associate Professor, 情報工学部, 助教授 (00322298)
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| Project Period (FY) |
2001 – 2003
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| Keywords | ILP / Processors / Reissue / Fault Tolerance / Speculation / Power / Critical Path / LSI |
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| Research Abstract |
Power consumption is a major concern in embedded microprocessors design.Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power..Regarding the effect of sustaining throughput on power and performance, it is found that pipelined functional units are better in energy reduction as well as in performance than non-pipelined units even if the increase in hardware due to extra latches are considered. We also evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is currently not a good design choice for energy efficiency.
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