2005 Fiscal Year Final Research Report Summary
Ultra Low Power GHz-Band RF DSP for Software Defined Radio Terminals
| Project/Area Number |
14205053
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Tohoku University |
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Principal Investigator |
TSUBOUCHI Kazuo Tohoku University, Research Institute of Electrical Communication, Professor, 電気通信研究所, 教授 (30006283)
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| Co-Investigator(Kenkyū-buntansha) |
NAKASE Hiroyuki Tohoku University, Research Institute of Electrical Communication, Associate Professor, 電気通信研究所, 助教授 (60312675)
KAMEDA Suguru Tohoku University, Research Institute of Electrical Communication, Research Associate, 電気通信研究所, 助手 (10343039)
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| Project Period (FY) |
2002 – 2005
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| Keywords | Software Defined Radio / Ultra Low Power / RF DSP / Currrent Mode Signal Processing / Spread Spectrum Communication / OFDM / FIR Filter / ASIC |
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| Research Abstract |
Software defined radio (SDR) is a promising solution for multi-mode and multi-band mobile communication system. One of key component of SDR is programmable filter, i.e., the radio frequency/immediate frequency band pass filter, the root roll off filter and so on. Although the recent digital signal processing (DSP) operates at high frequency, power of consumption of the filters using DSP is over 100mW.
We have already proposed and implemented the current-cut switched current matched filter (CC-SIMF). The power consumption of CC-SIMF can be remarkably reduced.
In this work, we propose the switched current analog programmable finite impulse response (FIR) filter for SDR terminals. New programmable tap circuits are proposed. Furthermore, implementation and measurement of the tap circuit are described and power consumption of 16-tap FIR filter is estimated.
For realizing flexible RF module, we propose a new concept of 3-D multilayer-stacked SiP. The new 3-D packaging concept includes (1) design guideline for interconnection lengths, (2) bridging register circuits in LSI chips, (3) flip-chip microbump bonding technology of chips onto system-buildup printed wiring boards (PWB), (4) multilayer-stacked 3-D package of several sets of chips and PWB, and (5)100-μm-diameter bumps at peripheral region of PWB as vertical via-bump bus lines.
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