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2004 Fiscal Year Final Research Report Summary

Si/SiGe Multiple-Barrier Resonant Tunneling Diode and Its Integrated Technology

Research Project

Project/Area Number 14350179
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionNational University Corporation Tokyo University of Agriculture and Technology

Principal Investigator

SUDA Yoshiyuki  Tokyo University of Agriculture & Technology, Information Media Center, Professor, 総合情報メディアセンター, 教授 (10226582)

Project Period (FY) 2002 – 2004
KeywordsSiGe / Resonant Tunneling Device / RTD / High Speed Device / Strain Relaxation / Quantum Well / PVCR / Multiple Barrier
Research Abstract

The head investigator has succeeded in fabricating a Si/SiGe resonant tunneling diode(RTD) which exhibits a peak-to-valley current ratio of as high as 7.6 in 1998 by applying a combination of electron tunneling and a multiple well structure on the basis of theoretical calculation. Further, we have proposed a thin double-layer strain-relaxed buffer as important technology for the electron-tunneling Si/SiGe RTD fabrication and have obtained a PVCR value of as high as〜180.
In this work, in order to realize quantum-effect high-speed Si-system devices, on the basis of these achievements, we aimed at establishing electron-tunneling Si/SiGe RTD device technology and basic technology for the device integration.
First, we have cleared the strain-relaxation mechanisms for the thin double-layer strain-relaxed buffer and its fabrication conditions. The 1st buffer layer grows coherently, however, upon 10-nm 2nd buffer layer growth, the 1st layer relaxes and the surface threading dislocation remains l … More ow. Thus, we have cleared that the 2nd buffer layer relaxes the 1st buffer layer and restrains the threading dislocations form propagating to the surface. On the basis of the results, we have further proposed a thin triple-layer buffer with which the positions of the lattice mismatch dislocation can be better controlled. We have cleared the fabrication principle and conditions. With the thin triple-layer buffer, we have a strain-relaxed buffer with high crystallinity and high relaxation rate, and have succeeded in fabricating high performance Si/SiGe RTD, the PVCR of which surpasses III-V RTDs. With these experimental results, we demonstrate that Si/SiGe quantum well tunneling structures are very useful as a practical device. Further, as basic integration technology, we have developed current density control method and device isolation technology.
Through these works, we have cleared the Si/SiGe RTD device construction technology and the basic integration technology such as device current control and device isolation technology. In this project, we have achieved the technological fundamentals for Si/SiGe electron-tunneling RTD device technology. Less

  • Research Products

    (17 results)

All 2004 2003 2002

All Journal Article (15 results) Book (1 results) Patent(Industrial Property Rights) (1 results)

  • [Journal Article] High PVCR Si/Si_<1-x>Ge_x DW RTD Formed with New Triple-Layer Buffer2004

    • Author(s)
      H.Maekawa, M.Shoji, Y.Suda
    • Journal Title

      Materials Science in Semiconductor Processing 8

      Pages: 417-421

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Ge Dot Array Formation Using Small Convex Position Anchors2004

    • Author(s)
      D.Kitayama, T.Yoshizawa, Y.Suda
    • Journal Title

      Jpn.J.Appl.Phys. 43

      Pages: 3822-3824

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Artificially Size- and Position-Controlled Ge Dot Formation Using Patterned Si2004

    • Author(s)
      Y.Suda, S.Kaechi, D.Kitayama, T.Yoshizawa
    • Journal Title

      Thin Solid Films 464-465

      Pages: 190-193

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] High PVCR Si/Si_<1-x>Ge_x DW RTD Formed with New Triple-Layer Buffer2004

    • Author(s)
      H.Maekawa, M.Shoji, Y.Suda
    • Journal Title

      Materials Science in Semiconductor Processing, vol.8

      Pages: 417-421

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Ge Dot Array Formation Using Small Convex Position Anchors2004

    • Author(s)
      D.Kitayama, T.Yoshizawa, Y.Suda
    • Journal Title

      Jpn.J.Appl.Phys. vol.43

      Pages: 3822-3824

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Artificially Size-and Position-Controlled Ge Dot Formation Using Patterned Si2004

    • Author(s)
      Y.Suda, S.Kaechi, D.Kitayama, T.Yoshizawa
    • Journal Title

      Thin Solid Films vol.464-465

      Pages: 190-193

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Si_<1-x>Ge_x Alloy Semiconductor2004

    • Author(s)
      Y.Suda
    • Journal Title

      Functional Materials, Experimental Chemistry Series(ed by T.Osaka, T.Honma and Y.Ito)(Maruzen, Tokyo)(in Japanese) vol.27

      Pages: 68-79

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Si Submonolayer and Monolayer Digital Growth Operation Technique Using Si_2H_6 as Atomically Controlled Growth Nanotechnology2003

    • Author(s)
      Y.Suda, N.Hosoya, K.Miki
    • Journal Title

      Appl.Surf.Sci. 216

      Pages: 424-430

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Si Submonolayer and Monolayer Digital Growth Operation Technique Using Si_2H_6 as Atomically Controlled Growth Nanotechnology2003

    • Author(s)
      Y.Suda, N.Hosoya, K.Miki
    • Journal Title

      Appl.Surf.Sci. vol.216

      Pages: 424-430

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Si_<1-x>Ge_x/Si Triple Barrier RTD with a High Peak-to-Valley Ratio of ≧ 180 at RT2002

    • Author(s)
      Y.Suda
    • Journal Title

      Elctrochemical Society Proceedings Volume PV2002-9

      Pages: 47-60

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] High PVCR Si_<1-x>Ge_x/Si Electron-Tunneling RTD Using Multiple-Well and Annealed Thin Double-Layer Buffer2002

    • Author(s)
      Y.Suda, A.Meguro, H.Maekawa
    • Journal Title

      Elctrochemical Society Proceedings Volume PV2002-17

      Pages: 118-127

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] New Si Atomic-Layer-Controlled Growth Technique with Thermally-Cracked Hydride Molecule2002

    • Author(s)
      Y.Suda, N.Hosoya, D.Shiratori
    • Journal Title

      Journal of Crystal Growth Vol.237-239

      Pages: 1404-1409

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Si1-xGex/Si Triple Barrier RTD with a High Peak-to-Valley Ratio of ≧ 180 at RT2002

    • Author(s)
      Y.Suda
    • Journal Title

      Electrochemical Society Proceedings Volume vol.PV 2002-9

      Pages: 47-60

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] High PVCR Si1-xGex/Si Electron-Tunneling RTD Using Multiple-Well and Annealed Thin Double-Layer Buffer2002

    • Author(s)
      Y.Suda, A.Meguro, H.Maekawa
    • Journal Title

      Electrochemical Society Proceedings Volume vol.PV 2002-17

      Pages: 118-127

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] New Si Atomic-Layer-Controlled Growth Technique with Thermally-Cracked Hydride Molecule2002

    • Author(s)
      Y.Suda, N.Hosoya, D.Shiratori
    • Journal Title

      Journal of Crystal Growth vol.237-239

      Pages: 1404-1409

    • Description
      「研究成果報告書概要(欧文)」より
  • [Book] 日本化学会編 実験化学講座 第27巻2004

    • Author(s)
      須田良幸 他
    • Total Pages
      465
    • Publisher
      丸善
    • Description
      「研究成果報告書概要(和文)」より
  • [Patent(Industrial Property Rights)] 半導体薄膜製造方法2004

    • Inventor(s)
      須田 良幸
    • Industrial Property Rights Holder
      東京農工大学
    • Industrial Property Number
      特願2004-253128
    • Filing Date
      2004-08-31
    • Description
      「研究成果報告書概要(和文)」より

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Published: 2006-07-11  

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