2003 Fiscal Year Final Research Report Summary
Low Power VLSI Design for Portable Multimedia Communication
| Project/Area Number |
14350203
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
情報通信工学
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| Research Institution | Osaka University |
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Principal Investigator |
ONOYE Takao ONOYE,Takao, 大学院・情報科学研究科, 教授 (60252590)
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| Co-Investigator(Kenkyū-buntansha) |
HATANAKA Masahide Dept. Information Systems Engineering, Assistant Professor, 大学院・情報科学研究科, 助手 (70346188)
MITSUYAMA Yukio Osaka University, Graduate School of Engineering, Assistant Professor, 大学院・工学研究科, 助手 (80346189)
FUJITA Gen Center for Advanced Science Innovation, Assistant Professor, 先端科学イノベーションセンター, 助手 (30304025)
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| Project Period (FY) |
2002 – 2003
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| Keywords | multimedia communication / VLSI / low power / 3D sound localization |
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| Research Abstract |
In this project, we developed a low power architecture for portable multimedia communication. We also attempted to implement VLSIs based on the architectures
We proposed a novel error concealment algorithm for the MPEG-4 video decoding. The proposed algorithm adopts a hybrid scheme, which can achieve consistent performance for various video sequences at various error rates, and can reduce computational complexity using the temporal and spatial correlation of macroblocks. The proposed algorithm is constructed on the basis of the MPEG-4 software decoder, and the experimental results demonstrate that our approach provides acceptable performance both subjectively and objectively at various bit error rates.
We devised a single DSP implementation of the realtime 3D sound synthesis, which is distinctive in that the audible frequency is divided into three so that an optimal filtering structure can be constructed differently for each subband to realize accurately HRTFs with practical memory size and computational costs.
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