2004 Fiscal Year Final Research Report Summary
Modeling of GaN-based Electron Devices
| Project/Area Number |
14550329
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Shibaura Institute of Technology |
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Principal Investigator |
HORIO Kazushi Shibaura Institute of Technology, Faculty of Systems Engineering, Professor, システム工学部, 教授 (10165590)
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| Project Period (FY) |
2002 – 2004
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| Keywords | GaN / FET / current collapse / drain lag / gate lag / trap / buffer layer / device simulation |
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| Research Abstract |
Recently, GaN-based FETs have received great interest because of their potential applications to high power and high temperature microwave devices. However, slow current transients are often observed even if the drain voltage or the gate voltage is changed abruptly. This is called drain lag or gate lag, and is problematic in circuit applications. The slow transients mean that the dc I-V curves and the ac I-V curves become quite different, resulting in lower ac power available than that expected from the dc operation. This is called power slump or current collapse in the GaN-device field. These are regarded as trap-related, and there are many experimental works reported on these phenomena. But, few theoretical works have been reported for GaN-based FETs
Therefore, in this work, two-dimensional transient simulations of GaN MESFETs have been performed in which a three level compensation model is adopted for the semi-insulating buffer layer where a shallow donor a deep donor, and a deep acc
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eptor are considered. Quasi-pulsed I-V curves have been derived from the transient characteristics. It has been shown that when the drain voltage is raised, the drain current overshoots the steady-state value, and when it is lowered, the drain current remains at a low value, showing drain-lag behavior. These are explained by the deep donor's electron capturing and electron emission processes. The drain lag has been shown to become a cause of current collapse, although some gate lag is also seen due to deep levels in the buffer layer. The current collapse has been shown to be more pronounced when the deep-acceptor density in the buffer layer is higher and when the off-state drain voltage is higher, because the trapping effects become more significant. These buffer-trapping effects may be similar to trapping effects in an undoped GaN layer in AlGaN/GaN HEMTs. It is concluded that to minimize the current collapse in GaN FETs, the (deep) acceptor density in the buffer layer should be made low. Less
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Research Products
(10 results)
