2014 Fiscal Year Annual Research Report
ゲルマニウム／ひずみーシリコンヘテロ接合を用いたトンネル電界効果トランジスタ
| Project/Area Number |
14J06072
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| Research Institution | The University of Tokyo |
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Principal Investigator |
金 ミンス 東京大学, 工学系研究科, 特別研究員(PD)
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| Project Period (FY) |
2014-04-25 – 2016-03-31
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| Keywords | Tunnel FET / Strain Engineering / Ge-source / MOS interface |
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| Outline of Annual Research Achievements |
I have proposed the hetero-junction TFET with simple structure including Ge-source/strained-Si-channel for high performance. I have optimized the fabrication processes and demonstrated the proposed Ge/sSOI TFETs with high performance of steep subthreshold swing and high Ion/Ioff ratio.
The effects of the strain engineering in the channel on the TFET's performance are experimentally confirmed for the first time. Moreover, the relationship between the MOS interface quality and TFET's performance was clarified.
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| Current Status of Research Progress |
Current Status of Research Progress
1: Research has progressed more than it was originally planned.
Reason
The research is proceeding according to plan.
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| Strategy for Future Research Activity |
1. Performance enhancement by back biasing
Recently, I have found the performance enhancement effect by back biasing. Therefore, The physical mechanism of the performance enhancement of TFET by the back biasing will be investigated and such effect will be used for further performance improvement.
2. Scaling the device size and EOT minimizing
Scaling the device size and EOT for maximizing device performances. Modification of the device structure and realization of high performance TFET with steep SS below 60 mV/dec and high Ion/Ioff ratio, comparable with that of advanced CMOS.
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Research Products
(7 results)
