2005 Fiscal Year Final Research Report Summary
Device Process for Integrated Systems Composed of Dislocation-Free III-V-N Alloys and Silicon
| Project/Area Number |
15002007
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| Research Category |
Grant-in-Aid for Specially Promoted Research
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| Allocation Type | Single-year Grants |
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| Review Section |
Science and Engineering
Engineering
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| Research Institution | Toyohashi University of Technology |
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Principal Investigator |
YONEZU Hiroo Toyohashi University of Technology, Dept. of Electrical and Electronic Engineering, Professor, 工学部, 教授 (90191668)
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| Co-Investigator(Kenkyū-buntansha) |
WAKAHARA Akihiro Toyohashi University of Technology, Dept. of Electrical and Electronic Engineering, Professor, 工学部, 教授 (00230912)
FURUKAWA Yuzo Toyohashi University of Technology, Dept. of Electrical and Electronic Engineering, Research Associate, 工学部, 助手 (20324486)
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| Project Period (FY) |
2003 – 2005
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| Keywords | III-V-N alloy / point defect / InGaPN / electric conductivity control / device process / MOS FET / light emitting diode / optoelectronic integrated system |
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| Research Abstract |
Basic process technologies have been developed for realizing novel optoelectronic integrated systems in a single chip, in which optical devices and electronic circuits were combined. These technologies were based on the dislocation-free heteroepitaxy of Si and III-V-N alloys.
We have investigated point defects originated in N atoms in the III-V-N alloys and optical and electronic properties related to the defects. The defects were decreased by rapid thermal annealing and by suppressing the irradiation of N ions generated in an rf-plasma source. The effects led to the increase in photoluminescence intensity and the reduction of Ga interstitials. In addition, InGaPN layers with direct transition were successfully grown. It was clarified that the defects cause poor electronic conductivity. N-and p-type electronic conductivities were controlled by S and Mg doping, respectively.
Si and III-V-N alloys were mutually impurities. Contamination during epitaxy was suppressed by applying a two-chamber molecular beam epitaxy system which was developed in this project. Process conditions for both devices of a Si MOS FET and a III-V-N alloy light emitting diode (LED) were optimized. Mutual diffusion between the Si and III-V-N alloy layers was suppressed by decreasing the growth temperature of a gate oxide. As a result, it became apparent that the novel optoelectronic integrated systems could be fabricated by applying a process flow followed to that of MOS integrated circuits.
The composite layer of Si/III-V-N alloy double heterostructure (DH) layers was grown on a Si substrate. Elemental devices for the integrated systems, MOS FETs and LEDs, were fabricated in the topmost Si layer and the III-V-N alloy DH layer, respectively by applying the process flow for the first time. The optical output of the LED was controlled by the MOS FET. These results mean that the basic device process technologies were developed for the novel integrated systems such as ultra-parallel networks and others.
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