2007 Fiscal Year Final Research Report Summary
High Performance Parallel Processor System Using Three-Dimensional Processor Chip
| Project/Area Number |
15106006
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| Research Category |
Grant-in-Aid for Scientific Research (S)
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| Allocation Type | Single-year Grants |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku University |
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Principal Investigator |
KOYANAGI Mitsumasa Tohoku University, Tohoku University, Graduate School of Engineering, Professor (60205531)
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| Co-Investigator(Kenkyū-buntansha) |
HANE Kazuhiro Tohoku University, Graduate School of Engineering, Professor (50164893)
SAMUKAWA Seiji Tohoku University, Graduate School of Engineering, Professor (30323108)
TANAKA Tetsu Tohoku University, Graduate School of Engineering, Associate Professor (40417382)
FUKUSHIMA Takafumi Tohoku University, Graduate School of Engineering, Assistant Professor (10374969)
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| Project Period (FY) |
2003 – 2007
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| Keywords | Three-Dimensionally Stacked Processor / Multiport Shared Memory / Three-Dimensional Integration / Wafer Bonding / Optical Interconnection / Optical Wave Guide / Parallel Processing System / High Speed Data Transfer |
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| Research Abstract |
A new parallel processing system with shared memories was proposed. We designed a prototype system and evaluated its performance. Data to be shared are transferred to processor elements (PE's) through a high-speed multiport ring bus in this system. An optical interconnection is used as the high-speed multiport ring bus. The system performance was improved by using node-shared cache memories with three-dimensional structure which decreases the cache miss-hit rate. The performance increased almost in proportion to the number of PE.
We developed two key technologies of optical interconnection and three-dimensional integration to realize the proposed system. We succeeded in fabricating the optical waveguide with an extremely low signal propagation loss of 0.029dB/cm. We achieved a high-speed data transfer rate of 10Gbps using this optical waveguide with the length of 5cm. We also developed a new beam-lead bonding technology to directly integrate photodetectors and VCSEL's on LSI chip. We fabricated a test module using these technologies in which SRAM cache memories were connected by this optical waveguide and confirmed the optical data transfer among these SRAM cache memories.
Furthermore, we developed a three-dimensional integration technology based on wafer bonding. We succeeded in fabricating a three-dimensionally stacked microprocessor test chip for the first time in the world. We also fabricated a three-dimensionally stacked memory test chip with ten memory layers. In addition, we developed a new three-dimensional integration technology called a super-chip integration technology aiming to realize a further advanced system with stacked microprocessor and memory chips. We could stack various kinds of chips with different chip size and thickness by the super-chip integration.
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