2006 Fiscal Year Final Research Report Summary
Research on high speed packet management with Reconfigurable Hardware
| Project/Area Number |
15300013
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | University of Tsukuba |
|---|
Principal Investigator |
YAMAGUCHI Yoshinori University of Tsukuba, Graduate School of Systems and Information Engineering, Professor, 大学院システム情報工学研究科, 教授 (00312827)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
MAEDA Atsushi University of Tsukuba, Graduate School of Systems and Information Engineering, Associate Professor, 大学院システム情報工学研究科, 助教授 (50293139)
TODA Kenji AIST, Information Technology Research Institute, Senior Researcher, 情報技術研究部門, 主任研究員 (70357565)
|
|---|
| Project Period (FY) |
2003 – 2006
|
| Keywords | Secure network / Intrusion detection system / FPGA / Nondeterministic Finite Automaton / encryption system |
|---|
| Research Abstract |
Attendant upon the acceleration of network, it is said to be difficult to develop network equipment which has the processing efficiency corresponding the speed of the network. In this research, we are going to develop network equipments which can accelerate the processing speed by using the rewritable semiconductor devices, such as FPGA.
As the first topic, research and development of the network IDS ( Intrusion Detection System) is studied, especially the efficient execution scheme of the system using FPGA devices is pursued. The system firstly forms the finite-state machine from IDS patterns, next it is converted to hardware description language automatically. The research themes for this topic are to develop the efficient execution processing scheme based on the FPGA devices with regarding the reduction of the hardware quantity. Finally, IDS experimental system which exceeds 10Gbps was made, by using the IDS pattern matching circuit based on the nondeterministic finite automaton (NFA). On this system the reduction of the circuit scale of FPGA is also realized. Furthermore, in order to do the further reduction of the hardware quantity of the FPGA circuit, more research is pursued by adopting a data compression technique to the circuit design.
As the second topic, we propose the reconfigurable system model which use FPGA to encrypt the data in the server-client encryption communication. In such a system, raising the availability of FPGA improves the performance. Therefore, it is important that the development of the prediction method to reducing useless reconfiguration of FPGA effectively. We propose the method of predicting the encryption algorithm used in the near future requests based on history of requests received so far to improve the efficiency of encryption. We employ the generalized n-gram model for that prediction, and verify its characteristics.
|
