2005 Fiscal Year Final Research Report Summary
Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit Techniques
| Project/Area Number |
15500029
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Tohoku University |
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Principal Investigator |
HANYU Takahiro Tohoku University, Research Institute of Electrical Communication, Professor, 電気通信研究所, 教授 (40192702)
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| Co-Investigator(Kenkyū-buntansha) |
MOCHIZUKI Akira Tohoku University, Research Institute of Electrical Communication, Research Assistant, 電気通信研究所, 助手 (40359542)
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| Project Period (FY) |
2003 – 2005
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| Keywords | information system / information communication engineering / electronic devices / equipments / semiconductor ultra-scaling / system-on-chip / network-on-chip / intra-chip high-speed signaling / multiple-valued encoding |
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| Research Abstract |
The trend in global interconnection delay such as clock distribution is becoming a significant problem in recent deep submicron VLSI. As CMOS technology scales from one generation to the next, the product of the interconnect resistance and load capacitance is not scaling with technology. One of the possible methods to solve the above interconnection problems is to use asynchronous circuit implementation. Dual-rail encoding is widely used as an encoding style of asynchronous data transfer, where every logical variable is encoded using two wires and timing information is also implicit in the code. Every asynchronous data transfer protocol is based on request-acknowledge handshaking : every transfer features a request action where the initiator starts a transfer, and an acknowledge action allowing the target to respond. In this way, the signals propagate round trip between the transmitter and the receiver, thus the cycle time of data transfer becomes large, which is the problem accompanyi
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ng asynchronous data transfer essentially. If the above procedures are executed simultaneously, the cycle time of the asynchronous data transfer with dual-rail encoding becomes much faster than that of the conventional methods. In this research, a new asynchronous data-transfer protocol, called 2-color "1-pbase" dual-rail encoding, is proposed for high-speed asynchronous data transfer. The 2-color 1-phase encoding has two colors which mean two kinds of data definition "ODD" and "EVEN", and different valid data is detected by transferring codewords which have different color alternately. In this protocol, the receiver as well as the transmitter sends the color information as the request signal, then the data transfer is performed by detecting whether the mutual color information is same or not. Because the both request signals can be sent simultaneously, overlap communication can be done. Since data and color information must be bundled on the same wires in the asynchronous data transfer, it is important to detect valid data from the mixed dual-rail code of data and color information. The use of the proposed encoding makes it easy to merge and detect data and color information by calculating the sum of the codewords. In multiple-valued bidirectional current-mode circuits, since current-mode linear summation can be implemented by wiring without any active devices, the proposed asynchronous circuit becomes simple. Moreover, current signals from both sides can be superposed on the same wires, which is an important characteristic of multiple-valued current-mode logic to realize a control signal multiplexing scheme. The use of comparators with sense amplifier makes it easy to detect the sum of components of the codewords quickly. In fact, it is evaluated in a 0.18um CMOS technology that the data transfer cycle of the proposed asynchronous data-transfer scheme using the multiple-valued current-mode logic circuit is about 1.5-times faster than that of the corresponding binary CMOS implementation under the normalized power dissipation. Less
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