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2005 Fiscal Year Final Research Report Summary

Study on Built-in Self Test and Fault Diagnosis for Very High Speed and Deep Sub-micron VLSIs

Research Project

Project/Area Number 15500043
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionEhime University

Principal Investigator

TAKAMATSU Yuzo  Ehime University, Faculty of Engineering, Professor, 工学部, 教授 (80039255)

Co-Investigator(Kenkyū-buntansha) TAKAHASHI Hiroshi  Ehime University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (80226878)
HIGAMI Yoshinobu  Ehime University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (40304654)
Project Period (FY) 2003 – 2005
KeywordsTesting of LSIs / Fault diagnosis / Built-in self test / Test compaction / Stuck-at fault / Internal bridging fault / Open fault
Research Abstract

We have developed a diagnostic test compaction method, a fault diagnostic method for open faults and a fault diagnostic method for internal bridging faults.
(1)Diagnostic test compaction method
In built-in self test of LSIs, a large number of test vectors must be applied. We have developed a method for selecting a small number of test vectors used for diagnosis of faulty LSIs. This method can reduce the execution time for fault diagnosis as well as memory space to store test data and output responses. The developed method selects a small number of test vectors among a given test set so that the number of fault pairs distinguished by the given test set is preserved. First, it extracts faults that are detected by only one test vector, and collect the test vectors that detect such faults. After that, a subset of fault pairs are selected and a small number of test vectors are selected so that the selected fault pairs are distinguished by the test vectors. The process of selection of fault pairs and test vectors is repeated until all the fault pairs are distinguished.
(2)Fault diagnostic method for open faults
We have developed a diagnostic method for open faults. In this research, we assumed that the value at a signal line with open fault is determined by adjacent signal lines. The developed method perform fault simulation using passing tests and failing tests, and deduces a small number of candidate faulty sites.
(3)Fault diagnostic method for internal bridging faults
We have developed a diagnostic method for internal bridging faults, which are caused by short between two transistor nodes. The developed method first performs logic simulation using passing tests in order to extract suspected faulty gates. Next, it deduces suspected internal bridging faults existing in the suspected faulty gates. Moreover, it reduces the suspected internal bridging faults by performing logic simulation using passing tests.

  • Research Products

    (6 results)

All 2006 2005

All Journal Article (6 results)

  • [Journal Article] Compaction of Pass/Fail-based Diagnostic Test Vectors for Combinational and Sequential Circuits2006

    • Author(s)
      Y.Higami, K.K.Saluji, H.Takahashi, S.Kobayashi, Y.Takamatsu
    • Journal Title

      Proc. of IEEE The Eleventh Asia and South Pacific Design Automation

      Pages: 659-664

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Compaction of Pass/Fail-based Diagnostic Test Vectors for Combinational and Sequential Circuits2006

    • Author(s)
      Y.Higami, K.K.Saluja, H.Takahashi, S.Kobayashi, Y.Takamatsu
    • Journal Title

      Proc.of IEEE Eleventh Asia and South Pacific Design Automation Conference

      Pages: 659-664

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] On the Fault Diagnosis in the Presence of Unknown Fault Models Using Pass/Fail Information2005

    • Author(s)
      Y.Takamatsu, T.Seiyama, H.Takahashi, Y.Higami, K.Yamazaki
    • Journal Title

      Proc. of IEEE Int. Sympo. on Circuits and Systems

      Pages: 2987-2990

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A Method for Reducing the Target Fault List of Crosstalk Faults in Synchronous Sequetial Circuits2005

    • Author(s)
      H.Takahashi, K.J.Keller, K.T.Le, K.K.Saluja, Y.Takamatsu
    • Journal Title

      IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems vol.24,no.2

      Pages: 252-263

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] On the Fault Diagnosis in the Presence of Unknown Fault Models Using Pass/Fail Information2005

    • Author(s)
      Y.Takamatsu, T.Seiyama, H.Takahashi, Y.Higami, K.Yamazaki
    • Journal Title

      Proc.of IEEE Int.Sympo. on Circuits and Systems

      Pages: 2987-2990

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A Method for Reducing the Target Fault List of Crosstalk Faults in Synchronous Sequential Circuits2005

    • Author(s)
      H.Takahashi, K.J.Keller, K.T.Le, K.K.Saluja, Y.Takamatsu
    • Journal Title

      IEEE Trans.on Computer-Aided Design of Integrated Circuits and Systems vol.24, no.2

      Pages: 252-263

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2007-12-13  

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