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2005 Fiscal Year Final Research Report Summary

Reconfigurable LSI Systems for Statistical Genetic Algorithms

Research Project

Project/Area Number 15500052
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionWaseda University

Principal Investigator

YANAGISAWA Masao  Waseda University, Faculty of Science and Engineering, Professor, 理工学術院, 教授 (30170781)

Project Period (FY) 2003 – 2005
KeywordsStatistical Genetics / LSI / Computer-Aided Design / FPGA
Research Abstract

The aim of this research is to develop a reconfigurable LSI system and LSI CAD (Computer-Aided Design) tools for statistical genetic algorithms. We have proposed a thread partitioning algorithm in low power high-level synthesis, a cosynthesis algorithm for applicaton specific processors with heterogeneous datapaths, instruction set and functional unit synthesis for SIMD processor cores, FPGA-based reconfigurable adaptive FEC, high-level power optimization based on thread partitioning, a hybrid dictionary test data compression for multiscan-based designs, a selective scan chain reconfiguration through run-length coding for test data compression and scan power reduction, a reconfigurable adaptive FEC system for reliable wireless communications, experimental evaluation of high-level energy optimization based on thread partitioning, a new correction for multiple comparisons in genome-wide case-control association studies based on haplotypes and diplotype configurations, a processor core synthesis system in IP-based SoC design, sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations, A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition, an interface-circuit synthesis method with configurable processor core in IP-based SoC designs, FCSCAN : an efficient multiscan-based test compression technique for test cost reduction, a fast elliptic curve cryptosystem LSI embedding word-based Montgomery multiplier, etc.Reconfigurable LSI systems for statistical genetic algorithms have not been developed yet, but enough technics to develop them areobtained in this research.

  • Research Products

    (40 results)

All 2006 2005 2004 2003

All Journal Article (40 results)

  • [Journal Article] An Interface-Circuit Synthesis Method with Configurable Processor Core in IP-Based SoC Designs2006

    • Author(s)
      S.Kohara et al.
    • Journal Title

      Proc. of ASP-DAC 2006

      Pages: 594-599

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] FCSCAN : An Efficient Multiscan-based Test Compression Technique for Test Cost Cost Reduction2006

    • Author(s)
      Y.Shi et al.
    • Journal Title

      Proc. of ASP-DAC 2006

      Pages: 653-658

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier2006

    • Author(s)
      J.Uchida et al.
    • Journal Title

      IEICE Trans. on Electronics E89-C, 3

      Pages: 243-249

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] An Interface-Circuit Synthesis Method with Configurable Processor Core in IP-Based SoC Designs2006

    • Author(s)
      S.Kohara et al.
    • Journal Title

      Proc.of ASP-DAC 2006

      Pages: 594-599

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] FCSCAN : An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction2006

    • Author(s)
      Y.Shi et al.
    • Journal Title

      Proc.of ASP-DAC 2006

      Pages: 653-658

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier2006

    • Author(s)
      J.Uchida et al.
    • Journal Title

      IEICE Trans.on Electronics E89-C, 3

      Pages: 243-249

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A Processor Core Synthesis System in IP-based SoC Design2005

    • Author(s)
      N.Tomono et al.
    • Journal Title

      Proc. of ASP-DAC 2005

      Pages: 286-291

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Sub-operation Parallelism Optimization in SIMD Processor Synthesis and Its Experimental Evaluations2005

    • Author(s)
      N.Togawa et al.
    • Journal Title

      IEICE Trans. on Fundamentals. E88-A, 4

      Pages: 876-884

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition2005

    • Author(s)
      N.Togawa et al.
    • Journal Title

      IEICE Trans. on Information and Systems E88-D, 7

      Pages: 1340-1349

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A Processor Core Synthesis System in IP-based SoC Design2005

    • Author(s)
      N.Tomono et al.
    • Journal Title

      Proc.of ASP-DAC 2005

      Pages: 286-291

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition2005

    • Author(s)
      N.Togawa et al.
    • Journal Title

      IEICE Trans.on Information and Systems E88-D, 7

      Pages: 1340-1349

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A Thread Partitioning Algorithm in Low Power High-Level Synthesis2004

    • Author(s)
      J.Uchida et al.
    • Journal Title

      Proc. ASP-DAC 2004

      Pages: 74-79

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A Cosynthesis Algorithm for Applicaton Specific Processors with Heterogeneous Datapaths2004

    • Author(s)
      Y.Miyaoka et al.
    • Journal Title

      Proc. ASP-DAC 2004

      Pages: 250-255

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Instruction Set and Functional Unit Synthesis for SIMD Processor Cores2004

    • Author(s)
      N.Togawa et al.
    • Journal Title

      Proc. ASP-DAC 2004

      Pages: 743-750

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Invader Assay 法の出力結果の自動クラスタリング手法・最短距離法を初期値としたMCMCによる手法2004

    • Author(s)
      間瀬洋一他
    • Journal Title

      人類遺伝学会シンポジウム

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] FPGA-B汗dReconfigurable Adaptive FEC2004

    • Author(s)
      K.Shimizu et al.
    • Journal Title

      IEICE Trans. on Fundamentals E87-A, 12

      Pages: 3036-3046

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] High-Level Power Optimization Based on thread Partitioning2004

    • Author(s)
      J.UChida et al.
    • Journal Title

      IEICE Trans. on Fundamentals E87-A, 12

      Pages: 3075-3082

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs2004

    • Author(s)
      Y.Shi et al.
    • Journal Title

      IEICE Trans. on Fundamentals E87-A, 12

      Pages: 3193-3199

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A Selective Scan Chain Reconfiguration th朗ghRun-Length Coding for Test Data Compression and Scan Power Reduction2004

    • Author(s)
      Y.Shi et al.
    • Journal Title

      IEICE Trans. on Fundamentals E87-A, 12

      Pages: 3208-3215

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A Reconfigurable Adaptive FEC System for Reliable Wireless Communications2004

    • Author(s)
      K.Shimizu et al.
    • Journal Title

      Proc. of Asia-Pacific Conference on Circuits and Systems

      Pages: 13-16

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Experimental Evaluation of High-Level Energy Optimization Based on Thread Partitioning2004

    • Author(s)
      J.Uchida et al.
    • Journal Title

      Proc. of Asia-Pacific Conference on Circuits and Systems

      Pages: 161-164

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A new correction for multiple comparisons in genome-wide case-control association studies based on haplotypes and diplotype configurations2004

    • Author(s)
      S.Fujii et al.
    • Journal Title

      13th Takeda Science Foundation Symposium on Bioscience

      Pages: 74

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A Thread Partitioning Algorithm in Low Power High-Level Synthesis2004

    • Author(s)
      J.Uchida et al.
    • Journal Title

      Proc.ASP-DAC 2004

      Pages: 74-79

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A Cosynthesis Algorithm for Application Specific Processors with Heterogeneous Datapaths2004

    • Author(s)
      Y.Miyaoka et al.
    • Journal Title

      Proc.ASP-DAC 2004

      Pages: 250-255

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Instruction Set and Functional Unit Synthesis for SIMD Processor Cores2004

    • Author(s)
      N.Togawa et al.
    • Journal Title

      Proc.ASP-DAC 2004

      Pages: 743-750

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] FPGA-Based Reconfigurable Adaptive FEC2004

    • Author(s)
      K.Shimizu et al.
    • Journal Title

      IEICE Trans.on Fundamentals E87-A, 12

      Pages: 3036-3046

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] High-Level Power Optimization Based on thread Partitioning2004

    • Author(s)
      J.Uchida et al.
    • Journal Title

      IEICE Trans.on Fundamentals E87-A, 12

      Pages: 3075-3082

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs2004

    • Author(s)
      Y.Shi et al.
    • Journal Title

      IEICE Trans.on Fundamentals E87-A, 12

      Pages: 3193-3199

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction2004

    • Author(s)
      Y.Shi et al.
    • Journal Title

      IEICE Trans.on Fundamentals E87-A, 12

      Pages: 3208-3215

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A Reconfigurable Adaptive FEC System for Reliable Wireless Communications2004

    • Author(s)
      K.Shimizu et al.
    • Journal Title

      Proc.of Asia-Pacific Conference on Circuits and Systems

      Pages: 13-16

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Experimental Evaluation of High-Level Energy Optimization Based on Thread Partitioning2004

    • Author(s)
      J.Uchida et al.
    • Journal Title

      Proc.of Asia-Pacific Conference on Circuits and Systems

      Pages: 161-164

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Sub-operation Parallelism Optimization in SIMD Processor Synthesis and Its Experimental Evaluations2004

    • Author(s)
      N.Togawa et al.
    • Journal Title

      IEICE Trans.on Fundamentals E88-A, 4

      Pages: 876-884

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] An Instruction-Set Simulator Generator for SIMD Processor Cores2003

    • Author(s)
      Y.Miyaoka et al.
    • Journal Title

      Proc. of SASIMI2003

      Pages: 160-167

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A Hardware/Software Cosynthesis System for Processor Cores with conternt Addressable Memories2003

    • Author(s)
      N.TOGAWA et al.
    • Journal Title

      IEICE Trans. on Fundamentals E86・A,5

      Pages: 1082-1092

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] A Parallel Alogrithm of GENEHUNTER on Multi-Processors2003

    • Author(s)
      Y.Mase et al.
    • Journal Title

      The American Journal of Human Genetics 73,5

      Pages: 474

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Idlight : A Fast Haplotype Inference Algorithm for Large-Scale Unphased Diploid Genotype Data based on EM Algorithm and Graph Theory2003

    • Author(s)
      K.Kajitani et al.
    • Journal Title

      The American Journal of Human Genetics 73,5

      Pages: 473

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] An Instruction-Set Simulator Generator for SIMD Processor Cores2003

    • Author(s)
      Y.Miyaoka et al.
    • Journal Title

      Proc.of SASIMI2003

      Pages: 160-167

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories2003

    • Author(s)
      N.Togawa et al.
    • Journal Title

      IEICE Trans.on Fundamentals E86-A, 5

      Pages: 1082-1092

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] A Parallel Algorithm of GENEHUNTER on Multi-Processors2003

    • Author(s)
      Y.Mase et al.
    • Journal Title

      The American Journal of Human Genetics 73, 5

      Pages: 474

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] ldlight : A Fast Haplotype Inference Algorithm for Large-Scale Unphased Diploid Genotype Data based on EM Algorithm and Graph Theory2003

    • Author(s)
      K.Kajitani et al.
    • Journal Title

      The American Journal of Human Genetics 73, 5

      Pages: 473

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2007-12-13  

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