2004 Fiscal Year Final Research Report Summary
Highly Parallel Network Processor Based on Self Timed Pipeline Circuit
| Project/Area Number |
15500056
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kochi University of Technology |
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Principal Investigator |
IWATA Makoto Kochi University of Technology, Dept.of Information Systems Engineering, Professor, 工学部, 教授 (60232683)
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| Project Period (FY) |
2003 – 2004
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| Keywords | Self-timed circuit / Data-driven architecture / Network processor / Class based QoS control / Packet classification / Signature matching / Macroflow model |
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| Research Abstract |
The objectives of this research project is to establish a flexible architecture of highly integrated network processor drip by exhaustively utilizing the self-timed pipeline as one of low-power, easily designed and high performance circuits. A part of the project has been conducted through developing and evaluating a newly designed LSI. The following basic research results have been obtained in this Project by applying the proposed architecture to the class based QoS control function like Diffserv and the high-level packet filtering such as that of firewall and intruder detection systam (IOS).
1 Self-Timed priocity queueing mechanism
We proposed a self-timed priority queueing mechanism in which every pair of stage of a folded pipeline has a bypass stage to minimize queueing delay time. We observed that the test chip fabricated by 0.18 um CMOS process could achieve around 100 M IP packets/s with 8 different classes.
2 Data-driven implementation of high-speed packet filtering
We proposed two data-driven implementations one is a static filtering of layer 4 packet header and the other one is a signature matching for payload inspection. Our evaluation results showed that 4 M packets/s for the static filtering and 0.1 M packets/s for the signature matching could be achieved on only one date-driven processor. Additional circuit cost of some dedicated instructions for the static filtering was evaluated by implementing a self-timed data-driven processor on FPGA. The result indicated that only 6 % increase of gates was enough to realize the proposed architecture.
3 Performance estimation model of the self-timed pipelined systems
We formulated a macro flow model by which the behavior of ever packet flowing in a self-timed pipeline can be modeled simply. Using this model, we can reduce simulation time of the self-timed pipelined systems in half with reasonable accuracy in comparison to the existing naive model.
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