2004 Fiscal Year Final Research Report Summary
Development of New FET-Type Ferroelectric Memory with an Intermediate Electrode
| Project/Area Number |
15560293
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Japan Advanced Institute of Science and Technology |
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Principal Investigator |
HORITA Susumu Japan Advanced Institute of Science and Technology, School of Materials Science, Associate Professor, 材料科学研究科, 助教授 (60199552)
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| Co-Investigator(Kenkyū-buntansha) |
NISHIOKA Kensuke Japan Advanced Institute of Science and Technology, School of Materials Science, Associate, 材料科学研究科, 助手 (00377441)
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| Project Period (FY) |
2003 – 2004
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| Keywords | Ferroelectric Memory / Silicon / PZT / Ferroelectric |
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| Research Abstract |
1.Reduction of Reading Voltage V_R
We used different electrode materials for the top and bottom electrodes of the ferroelectric PZT film in order to reduce e V_R. The bottom electrode is an intermediate electrode of Ir and the top electrodes are IrO_2, RuO_2 and PtO_x. The hysteresis loop of the PZT film was shifted toward positive electric field (E) in order of Ir-O_2, RuO_2 and PtO_x, which means that an inner E exists in the PZT films. Although this E reduces V_R, it assists the change of the remanent polarization, i.e., memory state, which is unfavorable for non-volatile memory.
2.Increase of Reading Number
This memory has one problem that the memory state is changed by reading because the remanent polarization sate is changed due to the leakage current through the off-state writing FET for reading. For this problem, we proposed one method that the electric intermediate point is connected to the drain region of the reading FET. By using this, the leakage current is reduced so that the reading number is increased by about one order than the conventional connection.
3.Fabrication of the Integrated circuits
We confirmed the principle operation of the integrated circuits of our new memory on an Si wafer under the conditions that the writing voltage was 5 V and the VR was 7 V. However, the difference on output voltage between two memory states was only 15 mV and very small. This is because the thickness of the YSZ film can be never thinned and the dielectric constant of the PZT film is large. Also, the gate leakage current flows largely. For these problems, we suggest one solution to use not only SiO_2 film with good interface property to Si instead of YSZ and but also ferroelectric materials with lower dielectric constant.
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Research Products
(8 results)
