Investigation of a substrate with both high heat exhausting and elctro magnetic noise sielding layer for power supply on chip applications

2017 Fiscal Year Final Research Report

• Project/Area Number: 15H03965
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Power engineering/Power conversion/Electric machinery
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: Matsumoto Satoshi 九州工業大学, 大学院工学研究院, 教授 (10577282)
• Co-Investigator(Kenkyū-buntansha): 長谷川 雅考 国立研究開発法人産業技術総合研究所, 材料・化学領域, 研究グループ長 (20357776) ; 馬場 昭好 九州工業大学, マイクロ化総合技術センター, 准教授 (80304872) ; 新海 聡子 九州工業大学, マイクロ化総合技術センター, 准教授 (90374785)
• Project Period (FY): 2015-04-01 – 2018-03-31
• Keywords: 集積化電源 / DCーDCコンバータ / POL / 小型電源

Outline of Final Research Achievements

Research and development trend for power supply is how to reduce the volume and power-SoC(Supply on Chip) is attracted attentions because it can ultimate miniaturization of the power supply. On the other hand, reduction in the size of the power supply has a limitation because of self-heating. In addition, it faces the problem electro magnetic noise. In this study, we develop process technology for implementing the heat exhaust structure and electro magnetic noise shielding layer.　We also clarify usefulness of these structure and magnetic noise shielding layer.

Free Research Field

集積システム