次世代電波望遠鏡用周波数解析装置の研究開発

2017 Fiscal Year Annual Research Report

• Project/Area Number: 15H05304
• Research Institution: Tokyo Institute of Technology
• Principal Investigator: 中原 啓貴 東京工業大学, 工学院, 准教授 (20624414)
• Project Period (FY): 2015-04-01 – 2019-03-31
• Keywords: FPGA / RNS / Radio Telescope / Deep Learning / CNN

Outline of Annual Research Achievements

剰余数系(RNS)を再帰的に繰り返し適用するNested RNS(NRNS)を考案し, 積和演算器の分割手法に適用する設計手法を考案した. また, NRNSに適した素数の組み合わせを発見した.
提案手法を ROACH2 FPGA ボードに実装し, テスト信号器を用いて評価する. 動作可能を確認した. 既存のハイエンドFPGAボード(Xilinx社VC707)にAD変換器を接続するボードを外注により開発し, 実装を行い, 提案手法の有効性を確認した.
また, 観測補助システムとして深層学習のFPGA実装に適した2値化Convolutional Neural Network (CNN)の学習方法と推論に適したハードウェア構成を研究開発し, Xilinx社Zynq UltraScale+ MPSoCボードに実装した. GPUと比較して電力性能効率に関して10倍優れていることを明らかにした.

Current Status of Research Progress

1: Research has progressed more than it was originally planned.

Reason

申請書と同程度の開発状況に達しており、観測補助システムに適した深層学習手法の開発に成功しているため。

Strategy for Future Research Activity

次世代プラットフォーム ROACH3 ボードの開発に協力し, デジタル信号器部分の開発を行う. SKA 計画で建築する次世代電波望遠鏡に提案手法を組込み, 観測を行う.
また, 研究成果を他の周波数解析装置（気象レーダ・CT スキャナ等）に転用・実用化する.
観測補助システムに適した深層学習のハードウェア化に取り組む.

Research Products

• [Journal Article] An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design (2018)
  • Author(s): Akira Jinguji, Shimpei Sato, Hiroki Nakahara
  • Journal Title: IEICE Transactions Volume: 101-D(2) Pages: 354-362
  • Peer Reviewed
• [Journal Article] A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA (2018)
  • Author(s): Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
  • Journal Title: IEICE Transactions Volume: 101-D(2) Pages: 376-386
  • Peer Reviewed
• [Journal Article] BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W (2018)
  • Author(s): Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
  • Journal Title: IEEE Journal of Solid-State Circuits Volume: 53(4) Pages: 983-994
  • Peer Reviewed
• [Presentation] A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA (2018)
  • Author(s): Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato
  • Organizer: FPGA
  • Int'l Joint Research
• [Presentation] A fully connected layer elimination for a binarizec convolutional neural network on an FPGA (2017)
  • Author(s): Hiroki Nakahara, Tomoya Fujii, Shimpei Sato
  • Organizer: FPL
  • Int'l Joint Research
• [Presentation] An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA (2017)
  • Author(s): Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato
  • Organizer: FPT
  • Int'l Joint Research
• [Presentation] On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA (2017)
  • Author(s): Haruyoshi Yonekawa, Hiroki Nakahara
  • Organizer: IPDPS Workshops
  • Int'l Joint Research
• [Presentation] A Random Forest Using a Multi-valued Decision Diagram on an FPGA (2017)
  • Author(s): Hiroki Nakahara, Akira Jinguji, Simpei Sato, Tsutomu Sasao
  • Organizer: ISMVL
  • Int'l Joint Research
• [Presentation] An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning (2017)
  • Author(s): Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura
  • Organizer: ARC
  • Int'l Joint Research