Study on Ordered Transactional Memory Supporting the Thread-Level Parallel Speculation

2017 Fiscal Year Final Research Report

• Project/Area Number: 15K00076
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Kyoto Institute of Technology
• Principal Investigator: HIRATA Hiroaki 京都工芸繊維大学, 情報工学・人間科学系, 准教授 (90273549)
• Co-Investigator(Kenkyū-buntansha): 布目 淳 京都工芸繊維大学, 情報工学・人間科学系, 助教 (60335320) ; 柴山 潔 京都情報大学院大学, その他の研究科, 教授 (70127091)
• Project Period (FY): 2015-10-21 – 2018-03-31
• Keywords: 計算機システム / ハイパフォーマンスコンピューティング / 投機実行 / スレッドレベル並列処理 / メモリシステム

Outline of Final Research Achievements

Many techniques for parallelizing a sequentially coded program have been developed and put to practical use. But still many program codes cannot be parallelized because it is impossible to assure that the candidate program for parallel execution produces the same results as the original program. To parallelize such programs, we have proposed speculative memory (SM) and developed an SM prototype system. With SM, programmers can specify the parallel and speculative execution of threads explicitly in their programs. The SM system manages the memory data that are speculatively read or written by the threads running in parallel. When the system detects inconsistent memory accesses, it recovers the computational state of the program and restarts the execution. Unless such inconsistencies often occur, the total execution time of the program can be shorter. Consequently, we could establish the fundamental of parallel speculation.

Free Research Field

情報工学