2017 Fiscal Year Final Research Report
Low temperature deposition of barrierless insulating film applicable to 3D and 2.5 D-IC
| Project/Area Number |
15K05975
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Kitami Institute of Technology |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
佐藤 勝 北見工業大学, 工学部, 助教 (10636682)
野矢 厚 北見工業大学, 工学部, 特任教授 (60133807)
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| Project Period (FY) |
2015-04-01 – 2018-03-31
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| Keywords | 3次元集積回路 / 絶縁膜 / シリコン貫通ビア配線 / 低温作製 / バリヤレス |
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| Outline of Final Research Achievements |
In the Si-semiconductor field, miniaturization in accordance with the conventional Moore's law is becoming difficult, and it is beginning to shift to a three-dimensional LSI that does not rely on miniaturization. In order to realize this, a through-silicon via (TSV) that connects chips or wafers in the shortest is indispensable.
In order to realize a three-dimensional integrated circuit with high yield, we cosider that the via-last process which fabricates the LSI first and then processes the TSV later is ideal, and the insulation barrier is heated to 200℃ or lower We examined for the purpose of functioning as an excellent barrier exhibiting good characteristics even at low temperatures and suppressing the diffusion of Cu even in the state where no diffusion barrier material is interposed and developing an excellent insulation barrier even at low temperature.
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| Free Research Field |
電気電子材料工学
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