Study on large capacitance circuits to integrate ultra-low-frequency analog signal processing circuits on a chip

2017 Fiscal Year Final Research Report

• Project/Area Number: 15K06047
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: 防衛大学校(総合教育学群、人文社会科学群、応用科学群、電気情報学群及びシステム工学群)
• Principal Investigator: Matsumoto Fujihiko 防衛大学校(総合教育学群、人文社会科学群、応用科学群、電気情報学群及びシステム工学群), 応用科学群, 教授 (10531767)
• Co-Investigator(Kenkyū-buntansha): 大淵 武史 防衛大学校(総合教育学群、人文社会科学群、応用科学群、電気情報学群及びシステム工学群), 応用科学群, 講師 (40582896)
• Project Period (FY): 2015-04-01 – 2018-03-31
• Keywords: 能動フィルタ / 超低周波フィルタ / 集積回路 / アナログ電子回路 / インピーダンススケーリング回路 / トランスコンダクタ / MOSFET / 生体医用電子回路

Outline of Final Research Achievements

Impedance scaling (IS) circuits based on current feedback theory to realize ultra-low-frequency integrated active filters have been developed for small-sized biomedical electronic devices. The main purpose is to reduce the offset voltages of fully differential filter employing symmetry-type floating impedance scaling (SFIS) circuits. The proposed technique is unifying a common-mode feedback (CMFB) circuits and the SFIS circuit unlike an ordinary way that the CMFB is combined with an OTA or an OPamp. In addition, other synthesizing techniques for low frequency filters with low offset voltages.

Free Research Field

電子回路