Research on High-Quality Test Method for Avoiding False Testing of Next-Generation Low-Power LSIs

2017 Fiscal Year Final Research Report

• Project/Area Number: 15K12003
• Research Category: Grant-in-Aid for Challenging Exploratory Research
• Allocation Type: Multi-year Fund
• Research Field: Computer system
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: Wen Xiaoqing 九州工業大学, 大学院情報工学研究院, 教授 (20250897)
• Co-Investigator(Kenkyū-buntansha): 梶原 誠司 九州工業大学, 大学院情報工学研究院, 教授 (80252592) ; 宮瀬 紘平 九州工業大学, 大学院情報工学研究院, 准教授 (30452824) ; Holst Stefan 九州工業大学, 大学院情報工学研究院, 助教 (40710322)
• Research Collaborator: Chakravarty K. ; Tehranipoor M. ; Girard P. ; Wunderlich H.-J. ; HAMADA Shuji ; Wang L.-T. ; Jan M. E. ; HADATE Koji
• Project Period (FY): 2015-04-01 – 2018-03-31
• Keywords: LSI回路 / スキャンテスト / テスト電力 / シフト電力 / IR-Drop / クロック / シフトエラー / 誤テスト

Outline of Final Research Achievements

This study points out that the root causes of false testing of low-power LSI circuits are (1) the unbalanced switching activity around clock trees for two adjacent flip-flops in a scan chain and (2) the excessive switching activity around long activated functional paths. From these unique observations, we propose a method called L-FTA: Layout-Level False Test Avoidance, which avoids possible false testing through sophisticated local layout adjustment for logic elements around clock trees and/or long sensitized functional paths. Extensive benchmark-circuit-based simulation and evaluation-based on test chips, the effectiveness of the proposed method has been confirmed. This novel high-quality LSI test technology is expected to significantly contribute to the creation of the next-generation low-power LSI cricuits.

Free Research Field

LSIテスト