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2017 Fiscal Year Annual Research Report

Study on high reliable processor based on mitigation and observation of aging

Research Project

Project/Area Number 15K15960
Research InstitutionNara Institute of Science and Technology

Principal Investigator

新谷 道広  奈良先端科学技術大学院大学, 情報科学研究科, 助教 (80748913)

Project Period (FY) 2015-04-01 – 2018-03-31
KeywordsMOSFET / プロセッサ設計 / 経年劣化 / NBTI / タイミング解析 / 回路シミュレーション
Outline of Annual Research Achievements

昨年度まで検討していた経年劣化見積もり手法は,あるワークロードを仮定して,そこから一意の信号確率を抽出して計算に用いていた.しかし,実際のプロセッサの稼働においては,常に一定ワークロードで動作しているわけではなく,常時刻々と変化している.したがって,単一のワークロードのみを考慮した場合だと,劣化により最悪遅延となるパスを見逃す可能性がある.さらにワークロードの推定はそれ自体が困難な課題である.本研究では,ワークロード依存の最悪ケースの劣化を,稀少事象を模擬する手法の1 つであるSubset simulation アルゴリズムを用いて高速に推定する手法を提案した.モンテカルロ・シミュレーションを適用した場合と比較して,計算時間を36 倍高速化できることを示した.

  • Research Products

    (16 results)

All 2018 2017 Other

All Journal Article (2 results) (of which Peer Reviewed: 2 results) Presentation (12 results) (of which Int'l Joint Research: 8 results) Remarks (2 results)

  • [Journal Article] Identification and Application of Invariant Critical Paths under NBTI Degradation2017

    • Author(s)
      Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E100-A Pages: 2797-2806

    • DOI

      10.1587/transfun.E100.A.2797

    • Peer Reviewed
  • [Journal Article] Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation2017

    • Author(s)
      Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E100-A Pages: 1464-1472

    • DOI

      10.1587/transfun.E100.A.1464

    • Peer Reviewed
  • [Presentation] Efficient Worst-case Timing Analysis of Critical-Path Delay under Workload-Dependent Aging Degradation2018

    • Author(s)
      Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
    • Int'l Joint Research
  • [Presentation] A Study on NBTI-induced Delay Degradation Considering Stress Frequency Dependence2018

    • Author(s)
      Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      International Symposium on Quality Electronic Design (ISQED)
    • Int'l Joint Research
  • [Presentation] Efficient Parameter-Extraction of SPICE Compact Model through Automatic Differentiation2018

    • Author(s)
      Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      IEEE International Conference on Microelectronic Test Structures (ICMTS)
    • Int'l Joint Research
  • [Presentation] Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence2018

    • Author(s)
      Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)
    • Int'l Joint Research
  • [Presentation] Area-Efficient Memristor-Crossbar-Based Error Correcting Code Circuit2018

    • Author(s)
      Mamoru Ishizaka, Michihiro Shintani, and Michiko Inoue
    • Organizer
      Workshop on Security, Reliability, Test, Privacy, Safety and Trust of Future Devices (SURREALIST)
    • Int'l Joint Research
  • [Presentation] A Golden-Free Hardware Trojan Detection Technique Considering Intra-Die Variation2018

    • Author(s)
      Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, and Alex Orailoglu
    • Organizer
      電子情報通信学会技術研究報告(ディペンダブルコンピューティング研究会)
  • [Presentation] メモリスタ論理による誤り訂正符号回路の設計と評価2018

    • Author(s)
      石坂守, 新谷道広, 井上美智子
    • Organizer
      電子情報通信学会技術研究報告(ディペンダブルコンピューティング研究会)
  • [Presentation] メモリスタニューラルネットワークにおける縮退故障による識別性能への影響2018

    • Author(s)
      石坂守, 新谷道広, 井上美智子
    • Organizer
      電子情報通信学会総合大会
  • [Presentation] LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations2017

    • Author(s)
      Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      ACM/IEEE Design Automation Conference (DAC)
    • Int'l Joint Research
  • [Presentation] Parameter Extraction for MOSFET Current Model Using Backward Propagation of Errors2017

    • Author(s)
      Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization (VMC)
    • Int'l Joint Research
  • [Presentation] Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection2017

    • Author(s)
      Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, and Alex Orailoglu
    • Organizer
      IEEE Asian Test Symposium (ATS)
    • Int'l Joint Research
  • [Presentation] トランジスタ劣化の永続・回復可能成分を考慮したしきい値電圧変動の時間依存モデル2017

    • Author(s)
      新瑞徳, 森田俊平, 新谷道広, 廣本正之, 佐藤高史
    • Organizer
      回路とシステムワークショップ (於 北九州国際会議場)
  • [Remarks] ディペンダブルシステム学研究室

    • URL

      http://dslab.naist.jp/

  • [Remarks] 個人ページ

    • URL

      https://sites.google.com/view/shintanimichihiro/

URL: 

Published: 2018-12-17  

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