2017 Fiscal Year Final Research Report
A Framework for FPGA-based Accelerators with Maximum Memory Performance
| Project/Area Number |
16K16026
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
|
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| Research Institution | Hokkaido University |
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Principal Investigator |
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| Project Period (FY) |
2016-04-01 – 2018-03-31
|
| Keywords | FPGA / 高位合成 / Python |
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| Outline of Final Research Achievements |
We developed a multi-paradigm high-level hardware design framework that easily exploits on-chip memory blocks and memory bandwidth of an FPGA. The framework is based on Veriloggen, a Python-based domain-specific language for hardware design. The newly developed framework supports 3 different programming paradigms; The compiler supports Sequential, Stream, and RTL. In addition to the framework, we developed a highly-abstracted dataflow-based hardware compiler for deep neural networks.
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| Free Research Field |
コンピュータアーキテクチャ
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