Stacked short channel III-V MOSFET

2017 Fiscal Year Final Research Report

• Project/Area Number: 16K18087
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Electron device/Electronic equipment
• Research Institution: Tokyo Institute of Technology
• Principal Investigator: Kanazawa Toru 東京工業大学, 工学院, 助教 (40514922)
• Project Period (FY): 2016-04-01 – 2018-03-31
• Keywords: MOSFET / 化合物半導体 / MOCVD / マルチゲート / ナノシート

Outline of Final Research Achievements

A transistor with vertically stacked InGaAs nanosheet channel was studied to realize the high-speed and low-power logic circuits. We proposed and demonstrated the fabrication process of InGaAs nanosheet channels, which were suspended by the heavily doped source/drain regrown by MOCVD. The cross-sectional observation showed that the two stacked InGaAs nanosheets had the thickness of 10 nm and width of 100 nm. After the formation of gate stacks with the high-k dielectric and molybdenum electrode, the transistor properties were measured. The I-V characteristics indicated the advantages of the stacked nanosheet structure.

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