2017 Fiscal Year Research-status Report
IoTセンサ向け802.11ahのPHY層の低コスト超低消費電力回路の開発
Project/Area Number |
16K18105
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Research Institution | Nara Institute of Science and Technology |
Principal Investigator |
Tran Thi・Hong 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (90760835)
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Project Period (FY) |
2016-04-01 – 2019-03-31
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Keywords | 802.11ah / Viterbi Decoder / Internet of Things / VLC / LLR / RLL |
Outline of Annual Research Achievements |
In year 2017 (H29), we have developed the Scrambler, Interleave, De-Interleave, and System Controller for 802.11ah PHY transceiver. We also wrote documents to explain about the design. In addition, we have proposed two methods to implement the encryption in PHY layer in order to increase security level for the transceiver. To check performance of proposed methods, we have written the simulators in Matlab. To broaden the research theme, we have proposed Log-Likelihood Ratio (LLR) calculation method and Join Polar and Run Length Limited (RLL) Decoding method for visible light communication system. In terms of research results, we have published (and will be published) 2 IEICE Letter papers, presented 2 invited talks and 5 regular oral talks in international workshop/conference, presented 3 papers in domestic technical reports.
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Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
In H29, we have followed the research planed made in H28. We have completed about 70% the plan. The remained tasks (such as developing Phase Tracking, etc.) will be done in next year H30. The delay of remained tasks is because we have prioritized the time for other research themes such as enhancing security level of 802.11ah, and improving performance of visible light communication system. In total, we self-evaluate to be “Progressing rather smoothly”.
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Strategy for Future Research Activity |
In the next school year H30, we plan to research on the following contents: [1] Developing Phase tracking and Auto Gained Control (AGC) of 802.11ah PHY layer. [2] Integrating these blocks into the developed blocks of PHY layer to build the first completed prototype of the 802.11ah PHY transceiver.
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Causes of Carryover |
To broaden the research theme, we have slightly changed the research plan of school year H29 (2017). In addition to developing the 802.11ah PHY transceiver (as plan), we also researched about improving security level of 802.11ah as well as increasing performance of VLC system. These researches have obtained some achievements. However, the original plan (only focus on 802.11ah transceiver) is delayed and some blocks such as Phase Tracking, Auto Gain Controlled, etc. are not developed yet. In H30 year, we plan to developed these blocks. The fund will be used for buying FPGA boards to test these blocks.
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Research Products
(13 results)