2007 Fiscal Year Final Research Report Summary
A Study on a multi-processor for multi-resolution processing in mobile applications
| Project/Area Number |
17300025
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Tokyo Metropolitan University (2006-2007)
Kochi University of Technology (2005) |
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Principal Investigator |
NISHITANI Takao Tokyo Metropolitan University, System Design Department, Professor (00389206)
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| Co-Investigator(Kenkyū-buntansha) |
IWATA Makoto Kochi University of Technology, Engineering Department, Professor (60232683)
SAKAI Keiichi Kochi University of Technology, Engineering Department, lecturer (90274117)
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| Project Period (FY) |
2005 – 2007
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| Keywords | Multi-resolution / Color Enhancement / Fine-to-coarse Processing / Foreground Separation / Super-Parallel DSP / Segment Bus / Systolic / FPGA |
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| Research Abstract |
In future, video information gathering through a camera on a mobile terminals becomes popular because camera modules become cheap. Howeve4 raw data through cameras are generally low SNR, and, therein, requires a lot of processing before actual use. The research target in this project consists of processing amount reduction for raw data handling by use of multi-resolution processing and the processor architecture establishment, which can wale up to TOPS (Ira Operations Per Second) processing capabffity under low power dissipation, with programmable capability for realizing a variety of applications. For raw data handling, color enhancement and foreground separation algorithms are evaluated for processing amount reduction by using multi-resolution. The color image enhancement uses single color element of H in the HSI color system, and it also employs wavelet transform for further reduction to 113. Foreground separation, using fine-to-coarse processing on Walsh spectrum domain, becomes stable and reduces the processing amount to only 10% of the original one. Both algorithms employs pixel wise processing including many conditional jump instructions, pipeline control of processors are not suitable, because of many NOP operations after JUMP instructions. As a result, a super-parallel DSP approach which does not employ pipeline control in every element processor is established for this purpose. The newly employed segment buses works quite well in block wise spatial operations, and it has been shown that segment bus approach is better than Systolic approach in terms of full search motion compensation. In order to reduce chip : sire, the clock frequency employed is set to the highest one under non-pipeline control As a preliminary hardware evaluation, FPGA implementation has been carried out and a single FPGAcan hold 96 DSPs of mid 1980s, resulting 50K gate count equivalently. A 1000K gate system will reach 280GOPS.
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Research Products
(35 results)
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[Presentation] IEICE SIP Technical Meeting2007
Author(s)
Takao, Nishitani, Motion Object Tracking by use of Walsh Spectrum Feature parameters
Organizer
IEICE SIP Technical Meeting
Place of Presentation
Yamaguchi
Year and Date
20070300
Description
「研究成果報告書概要(欧文)」より
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[Presentation] 低演算量カラー画像処理2006
Author(s)
千葉 晃宏、田岡 祐一、西谷 隆夫
Organizer
電子情報通信学会 SIPシンポジウム
Place of Presentation
京都大学
Year and Date
20061100
Description
「研究成果報告書概要(和文)」より
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