2006 Fiscal Year Final Research Report Summary
A Hardware Evaluation System for an Interconnection Network Using Reconfigurable Devices
| Project/Area Number |
17500051
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Okayama University of Science |
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Principal Investigator |
KOHATA Masaki Okayama University of Science, Faculty of Engineering, Professor, 工学部, 教授 (60170297)
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| Co-Investigator(Kenkyū-buntansha) |
UEJIMA Akira Okayama University of Science, Faculty of Engineering, Lecturer, 工学部, 講師 (30311781)
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| Project Period (FY) |
2005 – 2006
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| Keywords | Parallel Processing / Interconnection Network / FPGA / PC Cluster |
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| Research Abstract |
In this research, we designed and developed a network card for PC clusters using field programmable gate arrays (FPGA), and realized a PC cluster system with this card. This network card is a 32-bit PCI bus card and consists of one FPGA, two RAMs, and four connectors. The PCI interface, four communication ports, and a five-port switch are implemented in one FPGA, and the network configuration can be changed by reconfiguring the FPGA. The communication rate is recorded in one of the two RAMs, and the timing of events, such as communication start/end, are recorded in another RAM.
We developed software, including a device driver for the network card, communication library, and visualization tools. The device driver is implemented as a kernel module for the Linux OS. The communication library provides basic communication functions, such as initialize, finalize, send, receive, broadcast, and barrier synchronization. In addition, a reconfiguration tool was developed, which reconfigures the FPGA in each PC of the cluster from a management PC.
We used the card to construct a PC cluster system connected by a ring network. For system evaluation, measurement and comparison of communication performance were performed while changing the depth of the communication buffer by reconfiguring the FPGA. The communication rate and timing were measured and visualized at the execution of Jacobi method, using the card's communication log function.
In conclusion, the test confirmed the basic system functions. We are currently expanding the system to a two-dimensional lattice-type network.
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Research Products
(2 results)
