2006 Fiscal Year Final Research Report Summary
Investigation of high-k gate insulator and its interface property by contactless capacitance transient spectroscopy
| Project/Area Number |
17560012
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Applied materials science/Crystal engineering
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| Research Institution | University of Hyogo |
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Principal Investigator |
YOSHIDA Haruhiko University of Hyogo, Graduate School of Engineering, Associate Professor, 大学院工学研究科, 准教授 (90264837)
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| Co-Investigator(Kenkyū-buntansha) |
SATOH Shinichi University of Hyogo, Graduate School of Engineering, Professor, 大学院工学研究科, 教授 (80382258)
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| Project Period (FY) |
2005 – 2006
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| Keywords | high-k gate insulator / contactless characterization / scanning capacitance microscopy / capacitance-voltage method / interface trap |
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| Research Abstract |
In this research, we focused on electrical property of HfSiO/Si interface. First of all, the electrical properties of the HfSiO film of the various thickness were characterized by contactless C-V method. As a result, it was confirmed that a conventional C-V method could not be applied to the characterization of the ultra thin film sample with the thickness of 1.2 nm or less because of the leakage current. However, it was demonstrated that such an ultra thin film sample was able to be evaluated by using the contactless C-V method without receiving the influence of the leakage current.
Moreover, we have applied the scanning capacitance microscopy (SCM) measurements to the characterization of HfSiO/Si interfaces at a nanometer scale. As a result, we have demonstrated the validity of the SCM measurements with high sensitivity for high-k dielectrics/Si interfaces by comparing the distribution of interface traps before and after the H2 annealing.
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