2020 Fiscal Year Final Research Report
Development of high-level design methodology for security hardware based on redundant Galois-field arithmetic
Project/Area Number |
17H00729
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Research Category |
Grant-in-Aid for Scientific Research (A)
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Allocation Type | Single-year Grants |
Section | 一般 |
Research Field |
Computer system
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Research Institution | Tohoku University |
Principal Investigator |
Homma Naofumi 東北大学, 電気通信研究所, 教授 (00343062)
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Project Period (FY) |
2017-04-01 – 2021-03-31
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Keywords | 計算機システム / ハードウェアセキュリティ / LSI設計技術 |
Outline of Final Research Achievements |
In this research project, we have developed a design technology for the Galois-field arithmetic data path, which is the basis of cryptographic and error correction LSIs. First, (1) a formal design method for high-order arithmetic data paths based on redundant Galois field representations, such as polynomial ring representation and redundant representation basis, was developed, and (2) a formal verification method based on computer algebra applicable to the circuit representation was developed. We have then applied the formal design and verification method to the cryptographic processor data path as its application. In particular, we have designed and verified efficient and/or tamper-resistant processor data paths for the ISO / IEC international standard ciphers. Furthermore, (4) we have developed an automatic synthesis / verification system for higher-order Galois-field arithmetic data paths.
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Free Research Field |
計算機科学
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Academic Significance and Societal Importance of the Research Achievements |
ガロア体上の算術演算回路は,これまで設計者により経験的に設計されており,その検証に膨大な時間を必要としてきた.特に,実用的な暗号や誤り訂正回路の設計では,項数が100を越える長大なAND-XOR論理式が必要となり,シミュレーション用のテストベンチ作成も非直観的で困難であった.これに対して本研究では,新たな形式的表現を発案するとともに,グレブナー基底などの計算機代数の技法を駆使した形式的検証手法を開発した.これにより,従来困難だった規模の回路の完全な検証に実用的な時間で成功した.
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