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2021 Fiscal Year Final Research Report

Precise structure control of 3-dimensional integration CMOS using high mobility materials through layer transfer

Research Project

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Project/Area Number 17H06148
Research Category

Grant-in-Aid for Scientific Research (S)

Allocation TypeSingle-year Grants
Research Field Electronic materials/Electric materials
Research InstitutionThe University of Tokyo

Principal Investigator

Takagi Shinichi  東京大学, 大学院工学系研究科(工学部), 教授 (30372402)

Co-Investigator(Kenkyū-buntansha) 前田 辰郎  国立研究開発法人産業技術総合研究所, エレクトロニクス・製造領域, 研究主幹 (40357984)
入沢 寿史  国立研究開発法人産業技術総合研究所, エレクトロニクス・製造領域, 主任研究員 (40759940)
Project Period (FY) 2017-05-31 – 2022-03-31
KeywordsMOSFET / ゲルマニウム / III-V族化合物半導体 / 3次元集積 / 移動度 / 結晶ひずみ
Outline of Final Research Achievements

High-quality III-V-OI and GOI structures were formed on Si substrates using smart cut, epitaxial lift-off, and oxidation concentration methods, and ultra-thin III-V-OI nMOSFETs and GOI nMOSFETs/pMOSFETs with the thickness of 10 nm or less were realized by digital etching. The world's highest mobility was achieved by optimizing strain, surface orientation, and so on. We also proposed a low-resistance metal source-drain formation and its evaluation method, MOS interface control technologies to realize low interface defect densities. As a result, we established fundamental technologies for fabricating III-V/Ge 3-D stacked CMOS on Si substrates.

Free Research Field

半導体電子工学

Academic Significance and Societal Importance of the Research Achievements

継続的CMOSスケーリングとSi基板上の異種材料集積を用いたLSIシステムを可能にする、Si基板上のIII-V半導体やGe薄膜形成技術、高品質MOSFET作製技術を提供した。また、極薄膜チャネルMOSFETのキャリア輸送特性を明確にして、その決定機構を定量的に明らかにし、材料設計や素子設計上の指針を与えると共に、更なる性能向上のための新しいチャネルエンジニアリング手法を提案した。

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Published: 2023-01-30  

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