2017 Fiscal Year Annual Research Report
Embedded Compression for Embedded Intelligent Vision & Video System
| Project/Area Number |
17J10477
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| Research Institution | Waseda University |
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Principal Investigator |
郭 栗 早稲田大学, 理工学術院(情報生産システム研究科), 特別研究員(DC2)
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| Project Period (FY) |
2017-04-26 – 2019-03-31
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| Keywords | video coding / computer vision / embedded compression / power consumption |
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| Outline of Annual Research Achievements |
My research topic is "embedded compression for embedded intelligent vision & video system". Nowadays, video coding and computer vision algorithms are widely applied in mobile devices, such as smartphones and wireless sensor networks. While many of these devices are battery powered or even battery-less, a low energy consumption is crucial. In this research, I focus on reducing the dominant energy consumption of DRAM access by embedded compression.
DRAM access power is proportional to its volume, so it can be reduced by compressing data before storing them to DRAM and decompressing data after fetched back. Hence, I researched on the embedded compression for embedded video and vision systems. I published two journal and three international conference papers in this year.
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
DRAM access power is proportional to its volume, so it can be reduced by compressing data before storing them to DRAM and decompressing data after fetched back. The main DRAM access for computer vision algorithms includes the input images, the intermediate results of feature maps and the weight models. The compression of input images has been done before. Hence, for the latter two DRAM access, the two-year project is divided into four parts (P), including the compression of feature maps (P1), the compression of pre-trained weight models (P2), training based on the compressed weight models (P3), and hardware implementation of the above compression algorithms (P4). As scheduled for the first year, P1 and P2 have been finished, and some preparations for P3 have been done.
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| Strategy for Future Research Activity |
In the second year, the main works include:
<Part 3- training based on the compressed weights> to design the EC for weight in the training process. According to the study of 32-bit float training process, I will try to design a weight compression algorithm with a dynamic quantization. Moreover, for the training stage, some issues may be caused by applying lossy EC, more time will be spent on testing this work.
<Part 4- hardware implementation and efficient memory organization> to finish hardware implementations of EC, respectively for feature maps and weights. It contains the architecture design, RTL code writing, simulation, synthesis, the analysis of power dissipation and memory organization.
<Summary of this EC framework: finally, I will write a summary of this research.
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