2009 Fiscal Year Final Research Report
Vertical Integration of VLSI mobile processor for Wearable Perception Device
| Project/Area Number |
18200003
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kobe University |
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Principal Investigator |
YOSHIMOTO Masahiko Kobe University, 大学院・工学研究科, 教授 (30324099)
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| Co-Investigator(Kenkyū-buntansha) |
TUKAMOTO Masahiko 神戸大学, 大学院・工学研究科, 教授 (60273588)
ARIKI Yasuo 神戸大学, 都市安全研究センター (10135519)
TAKIGUCHI Tetuya 神戸大学, 大学院・工学研究科, 講師 (40397815)
KAWAGUCHI Hirosi 神戸大学, 大学院・工学研究科, 准教授 (00361642)
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| Project Period (FY) |
2006 – 2009
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| Keywords | 計算機アーキテクチャ / ウエアラブル / 画像認識 / 音声認識 / VLSI / プロセッサ |
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| Research Abstract |
The design technology of ultra-low power VLSI processor to improve the perception recognition ability of the next generation wearable computer has been developed. A SIFT Descriptor Generation Engine which features a VLSI oriented Scale Invariant Feature Transform (SIFT) algorithm was realized and it provides high energy efficiency, 2.79mJ/frame, and processing capability for HDTV resolution video (1920x1080 pixels) at 30 frames per second (fps). Moreover, the development of VLSI architecture for the real-time continuous speech recognition was completed about 20000 vocabularies.
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Research Products
(37 results)
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[Journal Article] A sub 100 mW H. 264 MP@L4. 1 Integer-pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-connected Systolic Array and Segmentation-free, Rectangle-access Search-window Buffer, IEICE Trans2008
Author(s)
Y. Murachi, J. Miyakoshi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, H. Kawaguchi, M. Yoshimoto
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Journal Title
Peer Reviewed
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