2009 Fiscal Year Final Research Report
Hardware approach for high-speed search algorithms with memory layer optimization
| Project/Area Number |
18300028
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Media informatics/Database
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| Research Institution | The University of Tokyo |
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Principal Investigator |
INABA Mary The University of Tokyo, 大学院・情報理工学系研究科, 准教授 (60282711)
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| Co-Investigator(Renkei-kenkyūsha) |
今井 浩 東京大学, 大学院・情報理工学系研究科, 教授 (80183010)
定兼 邦彦 国立情報学研究所, 情報学プリンシプル研究系, 准教授 (20323090)
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| Project Period (FY) |
2006 – 2009
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| Keywords | 超高速情報処理 / ディレクトリ・情報検索 / アルゴリズム / インターネット高速化 / コンテンツアーカイブ |
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| Research Abstract |
With the progress of semiconductor process technology, memory access gap, and thus, the pipeline stall time due to cache misses are increasing. It is often observed in the real world computation that the memory band width plays the role of computation bottleneck. Thus, considering memory hierarchy, it is important to hide the memory access latency with efficient utilization of upper layer memory. In this work, we propose and evaluate a hardware solution to accelerate for full text search with compressed succinct data structure. In addition, as a by-product, we propose an efficient prefetch method using memory map data structure.
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