2007 Fiscal Year Final Research Report Summary
Establishment of scaling technique of high-k gate dielectrics for low-power-consumption LSI
| Project/Area Number |
18360152
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Kyushu University |
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Principal Investigator |
NAKASHIMA Hiroshi Kyushu University, Art, Science and Technology Center for Cooperative Research, Professor (70172301)
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| Project Period (FY) |
2006 – 2007
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| Keywords | High permittivity insulating film / silicon / Electron cyclotron resonance / Low-power-consumption LSI / Hf oxide / Metal gate / TaN / Effective work function |
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| Research Abstract |
This subject aims to establish gate stack integration with metal-gate/high-k film/S_1 structure for future MOSFET with very low SiO_2 equivalent oxide thickness (EOT). The goals were the leakage current decrease of 6 orders relative to S_1O_2 with the same EOT and the same interface quality as SiO_2/Si The obtained results are summarized as follows:
1. SiO_2(15nm)/S_1 structure was first formed by thermal oxidation and subsequent etching Hf metal deposition and oxidation for SiO_2/S_1 structure were performed by using electron cyclotron resonance (ECR) plasma, which was followed by the post deposition annealing to induce the solid state reaction between HfO_x and SiO_2 As a results, EOT=115 nm and 4 orders decrease of leakage current could be achieved for fabricated TaN/HfO_2/HfSiO/S_1structure, Also, interface density (D_it) evaluation was performed by using DLTS, and D_it was 1× 10^<11>cm^<-2> eV^<-1>, which is similar to that of SiO_2/Si.
2.In order to establish process integration of metal gate, the etching methods and the effective work functions φ_eff of various metals such as Au, Pt, HfN, TaN, Al, and Hf on S_1O_2 and HfO_2 were studied in detail As a result, it was clarified that φ_eff for Au and Pt have high values of 5 0 eV, φ_eff for HfN and TaN have middle values of 4 5 eV, and cm for Al and Hf have low values 0.40 eV Through these investigations, the threshold voltage control for n-and p-channel MOSFET became possible.
3.The process integration for TaN/high-k/S_1-MOSFET was well established The fabricated MOSFET showed the normal operation Also, it was clarified that the degradation of interface quality and mobility caused by TaN deposition could be improved by relatively high temperature annealing.
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[Journal Article] Electrical Properties of TaN/Hf based-high-k/Si Gate Stack Structure2007
Author(s)
Y., Sugimoto, K., Yamamoto, M., Kajiwara, Y., Suehiro, H., Nakashima
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Journal Title
Engineering Sciences Reports Vol. 28, No. 4
Pages: 371-378
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Dependences of effective work functions of TaN on HfO_2 and S_1O_2 on post-metalization anneal2007
Author(s)
Y., Sugimoto, K., Yamamoto, M., Kajiwara, Y., Suehiro, D., Wang, H., Nakashima
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Journal Title
5th Int. Conf. Silicon Epitaxy and Heterostructures
Pages: 194-195
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Effective work function modulation of TaN metal gate on HfO_2 after post-metalization annealing2007
Author(s)
Y., Sugimoto, M., Kajiwara, K., Yamamoto, Y., Suehiro, D., Wang, H., Nakashima
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Journal Title
Applied Physics Letters Vol. 91, No. 11
Pages: 112105-3
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Fabrication of High-k Gate Dielectrics Using Plazma Oxidization and Post Deposition Anneal of Hf/S_1O_2 Si Structure2007
Author(s)
H., Nakashima, Y., Sugimoto, Y., Suehiro, M., Kajiwara, K., Yamamoto, D. Wang
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Journal Title
The 6th Int. Conf. Thin Film Physics and Application
Pages: 185
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and Post-deposition annealing of a Hf/S_1O_2/Si structure2006
Author(s)
Y., Sugimoto, H., Adachi, K., Yamamoto, D., Wang, H., Nakashima, H., Nakashima
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Journal Title
Materials Science in Semiconductor Processing No. 9
Pages: 1031-1036
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Fabrication of High-k Gate Dielectrics Using Plazma Oxidization and Post Deposition Anneal of Hf/SiO_2/Si Structure2007
Author(s)
H., Nakashima, Y., Sugimoto, Y., Suehiro, M., Kajiwara, K., Yamamoto, D., Wang
Organizer
The 6th Int. Conf. Thin Film Physics and Application
Place of Presentation
Shanghai, JiaotongUniv., China
Year and Date
2007-09-27
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Modulation of effective work function of Tae on HfO_2 and S_1O_2 by PDA treatments2007
Author(s)
M., Kajiwara, Y., Suehiro, Y., Sugimoto, D., Wang, H., Nakashima
Organizer
The 68th Meeting, Japan Society of Applied Physics
Place of Presentation
Hokkaido Institute of Technology
Year and Date
2007-09-06
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Fabrication of High-k gate dielectrics using plasma oxidation and subsequent PDA treatment of Hf/S_1O_2/Si structure2007
Author(s)
Y., Suehiro, Y., Sugimoto, M., Kajiwara, D., Wang, H., Nakashima
Organizer
The 68th Meeting, Japan Society of Applied Physics
Place of Presentation
Hokkaido Institute of Technology
Year and Date
2007-09-05
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Dependences of effective work functions of TaN on HfO_2 and SiO_2 on post-metalization anneal2007
Author(s)
Y., Sugimoto, K., Yamamoto, M., Kajiwara, Y., Suehiro, D., Wang, H., Nakashima
Organizer
5th Int. Conf. Silicon Epitaxy and Heterostructures
Place of Presentation
Marseille, France
Year and Date
2007-05-25
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Electrical Characterization of High-k Gate Dielectrics Fabricated Using Plasma Oxidization and Post Deposition Annealing of Hf/SiO_2/Si Structure2006
Author(s)
Y., Sugimoto, H., Adachi, K., Yamamoto, H., Nakashima, D., Wang, H., Nakashima
Organizer
Characterization of High-k Dielectric Materials
Place of Presentation
Nice, France
Year and Date
2006-06-01
Description
「研究成果報告書概要(欧文)」より
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