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2008 Fiscal Year Final Research Report

Software-Based Self-Test for Processors to guarantee high fault efficiency for structured faults

Research Project

  • PDF
Project/Area Number 18500038
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionNara Institute of Science and Technology

Principal Investigator

INOUE Michiko  Nara Institute of Science and Technology, 情報科学研究科, 准教授 (30273840)

Co-Investigator(Kenkyū-buntansha) OHTAKE Satoshi  奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20314528)
YONEDA Tomokazu  奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20359871)
Project Period (FY) 2006 – 2008
Keywords設計自動化 / VLSIのテスト / テスト容易化設計
Research Abstract

本研究では、機能テストと構造テストの特長を活かしたテスト手法である、プロセッサの命令レベル自己テスト法の研究を行った.パイプラインプロセッサに対し、モジュール単体でのテスト生成と命令列探索を組み合わせて効率のよいテスト生成手法を提案し、パス遅延故障に対し高い故障検出効率が得られることを示した.さらに、自己テストプログラムを効率よく生成する手法であるテンプレートを用いて生成された自己テストプログラムのためのテスト容易化設計手法を提案した提案法は、テンプレートレベル故障検出効率100%、すなわち、誤りマスクを完全に回避できることを特長とする.

  • Research Products

    (7 results)

All 2009 2008 2006

All Journal Article (2 results) (of which Peer Reviewed: 2 results) Presentation (5 results)

  • [Journal Article] Design for testability method to avoid error masking of software-based self-test for processors2008

    • Author(s)
      Masato Nakazato, Michiko Inoue, Satoshi Ohtake and Hideo Fujiwara
    • Journal Title

      IEICE Trans. on Information and Systems Vol.E91-D, No.3

      Pages: 763-770

    • Peer Reviewed
  • [Journal Article] Instruction-based self-testing of delay faults in pipelined processors2006

    • Author(s)
      Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara
    • Journal Title

      IEEE Trans. on Very Large Scale Integration(VLSI)Systems Vol.14, No.11

      Pages: 1203-1215

    • Peer Reviewed
  • [Presentation] Partial scan approach for secret information protection2009

    • Author(s)
      Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa and Hideo Fujiwara
    • Organizer
      Proceedings of the 14th IEEE European Test Symposium(ETS'09)
    • Year and Date
      20090500
  • [Presentation] Unsensitizable Path Identification at RTL Using High-Level Synthes is Information2009

    • Author(s)
      Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue, Hideo Fuji waral
    • Organizer
      Digest of papers of 16th IEEE International Test Synthesis Workshop
    • Year and Date
      20090000
  • [Presentation] "Delay test of FPGA routing networks by branched test paths, " Informal Digest of Papers2008

    • Author(s)
      Elena Hammari, Michiko Inoue, Einar J. Aas and Hideo Fujiwara
    • Organizer
      13th IEEE European Test Symposium(ETS'08)
    • Year and Date
      20080500
  • [Presentation] Design for testability of software-based self-test for processors2006

    • Author(s)
      Masato Nakazato, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara
    • Organizer
      15th IEEE Asian Test Symposium(ATS'06)
    • Year and Date
      20061100
  • [Presentation] プロセッサの命令レベル自己テストのためのテスト容易化設計2006

    • Author(s)
      中里昌人, 大竹哲史, 井上美智子, 藤原秀雄
    • Organizer
      信学技報(ICD2006-40~59)
    • Year and Date
      20060600

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Published: 2010-06-10   Modified: 2016-04-21  

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