Clarification of the guideline to improve SiC MOSFET performance based on the structural deformation analysis near the thermally-oxidized interface

2021 Fiscal Year Final Research Report

• Project/Area Number: 18H03771
• Research Category: Grant-in-Aid for Scientific Research (A)
• Allocation Type: Single-year Grants
• Section: 一般
• Review Section: Medium-sized Section 21:Electrical and electronic engineering and related fields
• Research Institution: The University of Tokyo
• Principal Investigator: KITA KOJI 東京大学, 大学院工学系研究科(工学部), 准教授 (00343145)
• Project Period (FY): 2018-04-01 – 2021-03-31
• Keywords: 電子・電気材料 / パワーデバイス / SiC / ゲート絶縁膜 / 界面準位 / 欠陥構造 / 格子歪み / 閾値電圧

Outline of Final Research Achievements

The problem with SiC power MOSFETs is that the guideline for performance improvement remains unclear because the limiting factors for channel characteristics are not yet clarified. In this study, we discovered a few previously unknown phenomena that occur at the SiO2/SiC interface during the formation of SiO2, the gate insulator, and elucidated the mechanisms of those phenomena. Examples of those phenomena are: anomalous distortion in SiC during the interface formation, and the change of band alignment between SiC and SiO2 caused by the introduction of nitrogen for the suppression of interface defects. The banefit of H2O vapor annealing of the interface was also clarified based on the evaluation of defect levels distributed inside of the SiO2 film. Based on these findings, we newly provided some guidelines for device process design.

Free Research Field

電子デバイス材料工学

Academic Significance and Societal Importance of the Research Achievements

MOSFETのチャネル特性は，ゲート絶縁膜とチャネル部分がつくる界面の品質で決まるが，S汎用的な手法で評価される指標である「界面準位密度」ではSiC-MOSFETの性能の善し悪しを反映しない。本研究では界面品質を従来通りの電気特性評価だけで決めるのを止め，界面近傍の数nmの空間の物性変化によって捉え直すことにより，新たにSiC中の異常な変化の発生やSiO2膜中の欠陥準位の増減を発見し系統的に解析した。これにより界面形成プロセスが与える，従来見落とされていた新たな効果を明確化している。これらの見解は，本研究内で既に提示したものに限らず，新たなSiCデバイス高性能化指針のヒントとなるものである。