2018 Fiscal Year Annual Research Report
酸化濃縮法を用いた高性能薄膜Ge-On-Insulator FETに関する研究
| Project/Area Number |
18J14311
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| Research Institution | The University of Tokyo |
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Principal Investigator |
JO KWANGWON 東京大学, 工学系研究科, 特別研究員(DC2)
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| Project Period (FY) |
2018-04-25 – 2020-03-31
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| Keywords | Ge / SiGe / GOI / Strain / Ge condnesantion / pMOSFET / ETB |
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| Outline of Annual Research Achievements |
Firstly, the effects of thinning SiGe thickness in the initial structures before Ge condensation have been quantitatively studied from the viewpoints of remaining strain and electric properties of GOI pMOSFET for improved Ge condensation method. Then, it is found that further high and uniform compressive strain through our proposal.We have systemically examined characteristics of strained SGOI pMOSFETs by Ge condensatio. Pure GOI pMOSFETs provide the maximum mobility because of band nature of Ge. The record hole mobility has been obtained for GOI pMOSFETs.
Next, in order to realize ETB (S)GOI pMOSFETs, 100 % GOI and SGOI with Ge fractions of 49 to 96 % were thinned by using plasma oxidation/etching and TMAH etching respectively. After thinning process, we have successfully formed uniform ETB SGOIs down to 2 nm or less. We have confirmed strain tendency as function GOI or SGOI thickness down to 0.5 nm, by thinning process. Then, we have fabricated strained ETB (S)GOI pMOSFET ranging from 10 to 2nm with high on/off ratio and high mobility in that Ge thickness. We have achieved great improvement of on/off ratio with thinner body. It is found that the present strained SGOI pMOSFETs provide the record hole mobility at tbody from 2 nm to 10 nm. In our case, record on/off ratio, which is even comparable with those of fin devices, has been obtained in the present devices with high strain and low crystal defect. Therefore, we could consider planar ETB GOI MOSFET is still promising as future logic devices.
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
Fabrication of GOI MOSFET on qulified substrate.
Based on former result (optimized GOI film), high performance UTB
GOI MOSFET will be fabricated. In addition, optimized process on front-gate structure will be established with technologies of the gate stacks, engineered channel (UTB, nanowire-Fin) formation, and low resistivity S/D formation. And then, these devices should be implemented on tensile strained SOI or <110> oriented SOI to obtain further improvement.
On the other hand, recently, we have developed tensiley strained GOI with lowering oxidation temperature. We can also expect to achieve high performance nMOSFET.
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| Strategy for Future Research Activity |
UTB GOI MOSFETs and multi gated GOI FETs such as Nanowire-FinFETs are quite promising device structures for the
future technology nodes. In order to sufficiently suppress the SCE, it is necessary to reduce the GOI thickness or their
dimension. Actually, the local Ge condensation is applicable to not only thinning planar channel but also narrowing 3-D
Ge channels, which are mandatory for advanced GOI FETs.
Also, <110>-oriented GOI film can be obtained by condensation technique using <110>-SOI substrates as a starting substrate. The <110> oriented planes theoretically offer the enhanced hole mobility. The highest mobility is obtained for channel along the <110> plane.
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