2019 Fiscal Year Research-status Report
HDLRuby: a new high productivity hardware description language targeting next generation edge computing architectures for IoT
| Project/Area Number |
18K11284
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| Research Institution | Ariake National College of Technology |
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Principal Investigator |
Gauthier Lovic 有明工業高等専門学校, 創造工学科, 准教授 (90535717)
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| Co-Investigator(Kenkyū-buntansha) |
石川 洋平 有明工業高等専門学校, 創造工学科, 准教授 (50435476)
白鳥 則郎 中央大学, 研究開発機構, 機構教授 (60111316)
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| Project Period (FY) |
2018-04-01 – 2022-03-31
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| Keywords | HDL / HW design / Translation / Evaluation / HW simulation / Edge computing |
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| Outline of Annual Research Achievements |
The goal of the research is to design a new hardware description language (HDL), named HDLRuby[1], aiming at improving the design productivity of hardware systems.
The previous year was dedicated to the design of the language core and the tools for generating synthesizable Verilog HDL or VHDL hardware description. The work of this year has been focused on four topics: the FPGA and IC implementation and evaluation of a processor design with HDLRuby as real-life case study; the implementation of several generic library components including final state machines, decoders and memories; the design of a new paradigm for a synthesizable unified implementation-independent communication system that allows to change the communication part of an HW component without requiring any reimplementation; the implementation of an RTL simulator for HDLRuby code.
Preliminary works have also been done for studying the introduction of edge computing support (as part of Internet of Things) in HDLRuby.
The works of the previous year lead to two publications:
[1] Evaluation of the HDLRuby Hardware Description Language by implementing an 8-bit RISC Processor
[2] A parallel implementation of deep neural networks distributed over multiple edge devices
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
The language was already fully usable in the previous year. This year it has been used for producing FPGA and IC implementations of HW described with HDLRuby, for extending the language with several libraries and a new paradigm, for implementing the simulation engine. The evaluation of the language showed that the produced HW has the same level of quality as standard VHDL RTL code while improving the productivity. This evaluation has been published as [1].
Works have also been done for introducing IoT and AI support in the language but they are still preliminary.
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| Strategy for Future Research Activity |
We plan to go on evaluating the new communication paradigm and actually implement IoT support in the language. It is also planned to implement a neuronal network library for HDLRuby as an application for evaluating the language on large scale applications.
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| Causes of Carryover |
It was planned to use all the grant amount for the year.
Unfortunately due the COVID-19 outbreak, the trip and attendance to the ICIAE conference for presenting the paper entitled "Evaluation of the HDLRuby Hardware Description Language by implementing an 8-bit RISC Processor" had to be cancelled.
(link: https://www2.ia-engineers.org/iciae2020/)
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