2020 Fiscal Year Research-status Report
HDLRuby: a new high productivity hardware description language targeting next generation edge computing architectures for IoT
| Project/Area Number |
18K11284
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| Research Institution | Ariake National College of Technology |
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Principal Investigator |
Gauthier Lovic 有明工業高等専門学校, 創造工学科, 准教授 (90535717)
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| Co-Investigator(Kenkyū-buntansha) |
石川 洋平 有明工業高等専門学校, 創造工学科, 准教授 (50435476)
白鳥 則郎 中央大学, 研究開発機構, 機構教授 (60111316)
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| Project Period (FY) |
2018-04-01 – 2022-03-31
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| Keywords | HDL / HW design / Framework / Libraries / Evaluation / Edgfe computing / Neural network |
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| Outline of Annual Research Achievements |
The goal of the research is to design a new hardware description language (HDL), named HDLRuby [1] aiming at improving the design productivity of hardware systems. The previous year was dedicated to the implementation of an RTL simulator for HDLRuby descriptions, design of libraries of generic components, and the evaluation of the FPGA and IC implementation from HDLRuby descriptions. This year, the framework of HDLRuby has been developed to a stable stage with a standalone interface, and new generic HW components libraries have been added including, seamless fixed point computation, abstract communications [2], linear algebra, and memories. Edge computing integration has been further investigated with the implementation in HDLRuby of a neural network library [3] and of a recurrent neural network cell [4]. For this last year, it is planned to focus on the FPGA implementation of IC using HDLRuby and explore the support of dynamic reconfiguration.
[1] https://rubygems.org/gems/HDLRuby
[2] Abstracting HW communications with channels for HDLRuby, ICIAE 2021 (Best presentation award)
[3] Rubyを基にしたハードウェア記述言語“HDLRuby”によるニューラルネットワークのハードウェア実装に関する検討, IEICE 2021
[4] HDLRubyによるハードウェアへの長・短期記憶の実装に関する検討, IEICE 2021
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
The language was already fully defined and used for real IC and FPGA designs in the previous years. This year it has been used for providing a standalone framework interface for HDLRuby, for extending the language with several new libraries and applications. The evaluation of the language showed that the design of complex circuit like deep learning neural networks, or support of various communication protocols, can be described with very few lines of code compared to standard hardware description languages [2][3][4].
Additional works include the seamless support of fixed point computations, linear algebra and generic memories.
While the implementation of the language, its framework and its libraries advanced smoothly, and while several publications have been done, the travel and meeting restrictions due to the COVID-19 did not allow us to promote the language as much as we expected.
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| Strategy for Future Research Activity |
We plan to focus more on the FPGA implementation of real-life circuits for edge computing using the HDLRuby framework and adding the support of dynamic reconfiguration.
For the promotion we plan to publish research papers in conferences, but we also expect to increase the exposure of the language by participating in a design contest.
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| Causes of Carryover |
The grant amount for the year has been used taking into account the travel restrictions (in practice, we them avoided as much as possible) due to the COVID-19 outbreak. However, a little part of the funds have been provisioned for buying licenses for HW synthesis tools for the next fiscal year.
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