2009 Fiscal Year Final Research Report
Multilevel Stabilizing Architecture for Overcoming Process Variation
| Project/Area Number |
19300012
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
NAKASHIMA Yasuhiko Nara Institute of Science and Technology, 情報科学研究科, 教授 (00314170)
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| Co-Investigator(Kenkyū-buntansha) |
YAMASHITA Shigeru 立命館大学, 情報理工学部・情報システム学科, 教授 (30362833)
NAKANISHI Masaki 山形大学, 地域教育文化学部・生活総合学科, 准教授 (40324967)
NAKADA Takashi 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (00452524)
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| Project Period (FY) |
2007 – 2009
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| Keywords | ハードウェア設計 |
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| Research Abstract |
We designed a group of basic cells with high capability of fault detection and propagation, and confirmed their superior effectiveness on robustness, area overhead and circuit delay through designing real LSI. Also we found the way to evaluate the overall reliability of function units that have plural faults, and developed a technique to improve the reliability by replacing basic cells with XOR cells. Moreover, we developed an 8way-VLIW processor equipped with an instruction decomposition mechanism that is inevitable for implementing processors with such high reliable basic cells, and confirmed the decomposition mechanism is feasible from the view point of area, IPC and circuit delay.
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